arch.go

Documentation: cmd/asm/internal/arch

     1  // Copyright 2015 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  // Package arch defines architecture-specific information and support functions.
     6  package arch
     7  
     8  import (
     9  	"cmd/internal/obj"
    10  	"cmd/internal/obj/arm"
    11  	"cmd/internal/obj/arm64"
    12  	"cmd/internal/obj/mips"
    13  	"cmd/internal/obj/ppc64"
    14  	"cmd/internal/obj/riscv"
    15  	"cmd/internal/obj/s390x"
    16  	"cmd/internal/obj/wasm"
    17  	"cmd/internal/obj/x86"
    18  	"fmt"
    19  	"strings"
    20  )
    21  
    22  // Pseudo-registers whose names are the constant name without the leading R.
    23  const (
    24  	RFP = -(iota + 1)
    25  	RSB
    26  	RSP
    27  	RPC
    28  )
    29  
    30  // Arch wraps the link architecture object with more architecture-specific information.
    31  type Arch struct {
    32  	*obj.LinkArch
    33  	// Map of instruction names to enumeration.
    34  	Instructions map[string]obj.As
    35  	// Map of register names to enumeration.
    36  	Register map[string]int16
    37  	// Table of register prefix names. These are things like R for R(0) and SPR for SPR(268).
    38  	RegisterPrefix map[string]bool
    39  	// RegisterNumber converts R(10) into arm.REG_R10.
    40  	RegisterNumber func(string, int16) (int16, bool)
    41  	// Instruction is a jump.
    42  	IsJump func(word string) bool
    43  }
    44  
    45  // nilRegisterNumber is the register number function for architectures
    46  // that do not accept the R(N) notation. It always returns failure.
    47  func nilRegisterNumber(name string, n int16) (int16, bool) {
    48  	return 0, false
    49  }
    50  
    51  // Set configures the architecture specified by GOARCH and returns its representation.
    52  // It returns nil if GOARCH is not recognized.
    53  func Set(GOARCH string) *Arch {
    54  	switch GOARCH {
    55  	case "386":
    56  		return archX86(&x86.Link386)
    57  	case "amd64":
    58  		return archX86(&x86.Linkamd64)
    59  	case "arm":
    60  		return archArm()
    61  	case "arm64":
    62  		return archArm64()
    63  	case "mips":
    64  		return archMips(&mips.Linkmips)
    65  	case "mipsle":
    66  		return archMips(&mips.Linkmipsle)
    67  	case "mips64":
    68  		return archMips64(&mips.Linkmips64)
    69  	case "mips64le":
    70  		return archMips64(&mips.Linkmips64le)
    71  	case "ppc64":
    72  		return archPPC64(&ppc64.Linkppc64)
    73  	case "ppc64le":
    74  		return archPPC64(&ppc64.Linkppc64le)
    75  	case "riscv64":
    76  		return archRISCV64()
    77  	case "s390x":
    78  		return archS390x()
    79  	case "wasm":
    80  		return archWasm()
    81  	}
    82  	return nil
    83  }
    84  
    85  func jumpX86(word string) bool {
    86  	return word[0] == 'J' || word == "CALL" || strings.HasPrefix(word, "LOOP") || word == "XBEGIN"
    87  }
    88  
    89  func jumpRISCV(word string) bool {
    90  	switch word {
    91  	case "BEQ", "BEQZ", "BGE", "BGEU", "BGEZ", "BGT", "BGTU", "BGTZ", "BLE", "BLEU", "BLEZ",
    92  		"BLT", "BLTU", "BLTZ", "BNE", "BNEZ", "CALL", "JAL", "JALR", "JMP":
    93  		return true
    94  	}
    95  	return false
    96  }
    97  
    98  func jumpWasm(word string) bool {
    99  	return word == "JMP" || word == "CALL" || word == "Call" || word == "Br" || word == "BrIf"
   100  }
   101  
   102  func archX86(linkArch *obj.LinkArch) *Arch {
   103  	register := make(map[string]int16)
   104  	// Create maps for easy lookup of instruction names etc.
   105  	for i, s := range x86.Register {
   106  		register[s] = int16(i + x86.REG_AL)
   107  	}
   108  	// Pseudo-registers.
   109  	register["SB"] = RSB
   110  	register["FP"] = RFP
   111  	register["PC"] = RPC
   112  	if linkArch == &x86.Linkamd64 {
   113  		// Alias g to R14
   114  		register["g"] = x86.REGG
   115  	}
   116  	// Register prefix not used on this architecture.
   117  
   118  	instructions := make(map[string]obj.As)
   119  	for i, s := range obj.Anames {
   120  		instructions[s] = obj.As(i)
   121  	}
   122  	for i, s := range x86.Anames {
   123  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   124  			instructions[s] = obj.As(i) + obj.ABaseAMD64
   125  		}
   126  	}
   127  	// Annoying aliases.
   128  	instructions["JA"] = x86.AJHI   /* alternate */
   129  	instructions["JAE"] = x86.AJCC  /* alternate */
   130  	instructions["JB"] = x86.AJCS   /* alternate */
   131  	instructions["JBE"] = x86.AJLS  /* alternate */
   132  	instructions["JC"] = x86.AJCS   /* alternate */
   133  	instructions["JCC"] = x86.AJCC  /* carry clear (CF = 0) */
   134  	instructions["JCS"] = x86.AJCS  /* carry set (CF = 1) */
   135  	instructions["JE"] = x86.AJEQ   /* alternate */
   136  	instructions["JEQ"] = x86.AJEQ  /* equal (ZF = 1) */
   137  	instructions["JG"] = x86.AJGT   /* alternate */
   138  	instructions["JGE"] = x86.AJGE  /* greater than or equal (signed) (SF = OF) */
   139  	instructions["JGT"] = x86.AJGT  /* greater than (signed) (ZF = 0 && SF = OF) */
   140  	instructions["JHI"] = x86.AJHI  /* higher (unsigned) (CF = 0 && ZF = 0) */
   141  	instructions["JHS"] = x86.AJCC  /* alternate */
   142  	instructions["JL"] = x86.AJLT   /* alternate */
   143  	instructions["JLE"] = x86.AJLE  /* less than or equal (signed) (ZF = 1 || SF != OF) */
   144  	instructions["JLO"] = x86.AJCS  /* alternate */
   145  	instructions["JLS"] = x86.AJLS  /* lower or same (unsigned) (CF = 1 || ZF = 1) */
   146  	instructions["JLT"] = x86.AJLT  /* less than (signed) (SF != OF) */
   147  	instructions["JMI"] = x86.AJMI  /* negative (minus) (SF = 1) */
   148  	instructions["JNA"] = x86.AJLS  /* alternate */
   149  	instructions["JNAE"] = x86.AJCS /* alternate */
   150  	instructions["JNB"] = x86.AJCC  /* alternate */
   151  	instructions["JNBE"] = x86.AJHI /* alternate */
   152  	instructions["JNC"] = x86.AJCC  /* alternate */
   153  	instructions["JNE"] = x86.AJNE  /* not equal (ZF = 0) */
   154  	instructions["JNG"] = x86.AJLE  /* alternate */
   155  	instructions["JNGE"] = x86.AJLT /* alternate */
   156  	instructions["JNL"] = x86.AJGE  /* alternate */
   157  	instructions["JNLE"] = x86.AJGT /* alternate */
   158  	instructions["JNO"] = x86.AJOC  /* alternate */
   159  	instructions["JNP"] = x86.AJPC  /* alternate */
   160  	instructions["JNS"] = x86.AJPL  /* alternate */
   161  	instructions["JNZ"] = x86.AJNE  /* alternate */
   162  	instructions["JO"] = x86.AJOS   /* alternate */
   163  	instructions["JOC"] = x86.AJOC  /* overflow clear (OF = 0) */
   164  	instructions["JOS"] = x86.AJOS  /* overflow set (OF = 1) */
   165  	instructions["JP"] = x86.AJPS   /* alternate */
   166  	instructions["JPC"] = x86.AJPC  /* parity clear (PF = 0) */
   167  	instructions["JPE"] = x86.AJPS  /* alternate */
   168  	instructions["JPL"] = x86.AJPL  /* non-negative (plus) (SF = 0) */
   169  	instructions["JPO"] = x86.AJPC  /* alternate */
   170  	instructions["JPS"] = x86.AJPS  /* parity set (PF = 1) */
   171  	instructions["JS"] = x86.AJMI   /* alternate */
   172  	instructions["JZ"] = x86.AJEQ   /* alternate */
   173  	instructions["MASKMOVDQU"] = x86.AMASKMOVOU
   174  	instructions["MOVD"] = x86.AMOVQ
   175  	instructions["MOVDQ2Q"] = x86.AMOVQ
   176  	instructions["MOVNTDQ"] = x86.AMOVNTO
   177  	instructions["MOVOA"] = x86.AMOVO
   178  	instructions["PSLLDQ"] = x86.APSLLO
   179  	instructions["PSRLDQ"] = x86.APSRLO
   180  	instructions["PADDD"] = x86.APADDL
   181  
   182  	return &Arch{
   183  		LinkArch:       linkArch,
   184  		Instructions:   instructions,
   185  		Register:       register,
   186  		RegisterPrefix: nil,
   187  		RegisterNumber: nilRegisterNumber,
   188  		IsJump:         jumpX86,
   189  	}
   190  }
   191  
   192  func archArm() *Arch {
   193  	register := make(map[string]int16)
   194  	// Create maps for easy lookup of instruction names etc.
   195  	// Note that there is no list of names as there is for x86.
   196  	for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
   197  		register[obj.Rconv(i)] = int16(i)
   198  	}
   199  	// Avoid unintentionally clobbering g using R10.
   200  	delete(register, "R10")
   201  	register["g"] = arm.REG_R10
   202  	for i := 0; i < 16; i++ {
   203  		register[fmt.Sprintf("C%d", i)] = int16(i)
   204  	}
   205  
   206  	// Pseudo-registers.
   207  	register["SB"] = RSB
   208  	register["FP"] = RFP
   209  	register["PC"] = RPC
   210  	register["SP"] = RSP
   211  	registerPrefix := map[string]bool{
   212  		"F": true,
   213  		"R": true,
   214  	}
   215  
   216  	// special operands for DMB/DSB instructions
   217  	register["MB_SY"] = arm.REG_MB_SY
   218  	register["MB_ST"] = arm.REG_MB_ST
   219  	register["MB_ISH"] = arm.REG_MB_ISH
   220  	register["MB_ISHST"] = arm.REG_MB_ISHST
   221  	register["MB_NSH"] = arm.REG_MB_NSH
   222  	register["MB_NSHST"] = arm.REG_MB_NSHST
   223  	register["MB_OSH"] = arm.REG_MB_OSH
   224  	register["MB_OSHST"] = arm.REG_MB_OSHST
   225  
   226  	instructions := make(map[string]obj.As)
   227  	for i, s := range obj.Anames {
   228  		instructions[s] = obj.As(i)
   229  	}
   230  	for i, s := range arm.Anames {
   231  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   232  			instructions[s] = obj.As(i) + obj.ABaseARM
   233  		}
   234  	}
   235  	// Annoying aliases.
   236  	instructions["B"] = obj.AJMP
   237  	instructions["BL"] = obj.ACALL
   238  	// MCR differs from MRC by the way fields of the word are encoded.
   239  	// (Details in arm.go). Here we add the instruction so parse will find
   240  	// it, but give it an opcode number known only to us.
   241  	instructions["MCR"] = aMCR
   242  
   243  	return &Arch{
   244  		LinkArch:       &arm.Linkarm,
   245  		Instructions:   instructions,
   246  		Register:       register,
   247  		RegisterPrefix: registerPrefix,
   248  		RegisterNumber: armRegisterNumber,
   249  		IsJump:         jumpArm,
   250  	}
   251  }
   252  
   253  func archArm64() *Arch {
   254  	register := make(map[string]int16)
   255  	// Create maps for easy lookup of instruction names etc.
   256  	// Note that there is no list of names as there is for 386 and amd64.
   257  	register[obj.Rconv(arm64.REGSP)] = int16(arm64.REGSP)
   258  	for i := arm64.REG_R0; i <= arm64.REG_R31; i++ {
   259  		register[obj.Rconv(i)] = int16(i)
   260  	}
   261  	// Rename R18 to R18_PLATFORM to avoid accidental use.
   262  	register["R18_PLATFORM"] = register["R18"]
   263  	delete(register, "R18")
   264  	for i := arm64.REG_F0; i <= arm64.REG_F31; i++ {
   265  		register[obj.Rconv(i)] = int16(i)
   266  	}
   267  	for i := arm64.REG_V0; i <= arm64.REG_V31; i++ {
   268  		register[obj.Rconv(i)] = int16(i)
   269  	}
   270  
   271  	// System registers.
   272  	for i := 0; i < len(arm64.SystemReg); i++ {
   273  		register[arm64.SystemReg[i].Name] = arm64.SystemReg[i].Reg
   274  	}
   275  
   276  	register["LR"] = arm64.REGLINK
   277  	register["DAIFSet"] = arm64.REG_DAIFSet
   278  	register["DAIFClr"] = arm64.REG_DAIFClr
   279  	register["PLDL1KEEP"] = arm64.REG_PLDL1KEEP
   280  	register["PLDL1STRM"] = arm64.REG_PLDL1STRM
   281  	register["PLDL2KEEP"] = arm64.REG_PLDL2KEEP
   282  	register["PLDL2STRM"] = arm64.REG_PLDL2STRM
   283  	register["PLDL3KEEP"] = arm64.REG_PLDL3KEEP
   284  	register["PLDL3STRM"] = arm64.REG_PLDL3STRM
   285  	register["PLIL1KEEP"] = arm64.REG_PLIL1KEEP
   286  	register["PLIL1STRM"] = arm64.REG_PLIL1STRM
   287  	register["PLIL2KEEP"] = arm64.REG_PLIL2KEEP
   288  	register["PLIL2STRM"] = arm64.REG_PLIL2STRM
   289  	register["PLIL3KEEP"] = arm64.REG_PLIL3KEEP
   290  	register["PLIL3STRM"] = arm64.REG_PLIL3STRM
   291  	register["PSTL1KEEP"] = arm64.REG_PSTL1KEEP
   292  	register["PSTL1STRM"] = arm64.REG_PSTL1STRM
   293  	register["PSTL2KEEP"] = arm64.REG_PSTL2KEEP
   294  	register["PSTL2STRM"] = arm64.REG_PSTL2STRM
   295  	register["PSTL3KEEP"] = arm64.REG_PSTL3KEEP
   296  	register["PSTL3STRM"] = arm64.REG_PSTL3STRM
   297  
   298  	// Conditional operators, like EQ, NE, etc.
   299  	register["EQ"] = arm64.COND_EQ
   300  	register["NE"] = arm64.COND_NE
   301  	register["HS"] = arm64.COND_HS
   302  	register["CS"] = arm64.COND_HS
   303  	register["LO"] = arm64.COND_LO
   304  	register["CC"] = arm64.COND_LO
   305  	register["MI"] = arm64.COND_MI
   306  	register["PL"] = arm64.COND_PL
   307  	register["VS"] = arm64.COND_VS
   308  	register["VC"] = arm64.COND_VC
   309  	register["HI"] = arm64.COND_HI
   310  	register["LS"] = arm64.COND_LS
   311  	register["GE"] = arm64.COND_GE
   312  	register["LT"] = arm64.COND_LT
   313  	register["GT"] = arm64.COND_GT
   314  	register["LE"] = arm64.COND_LE
   315  	register["AL"] = arm64.COND_AL
   316  	register["NV"] = arm64.COND_NV
   317  	// Pseudo-registers.
   318  	register["SB"] = RSB
   319  	register["FP"] = RFP
   320  	register["PC"] = RPC
   321  	register["SP"] = RSP
   322  	// Avoid unintentionally clobbering g using R28.
   323  	delete(register, "R28")
   324  	register["g"] = arm64.REG_R28
   325  	registerPrefix := map[string]bool{
   326  		"F": true,
   327  		"R": true,
   328  		"V": true,
   329  	}
   330  
   331  	instructions := make(map[string]obj.As)
   332  	for i, s := range obj.Anames {
   333  		instructions[s] = obj.As(i)
   334  	}
   335  	for i, s := range arm64.Anames {
   336  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   337  			instructions[s] = obj.As(i) + obj.ABaseARM64
   338  		}
   339  	}
   340  	// Annoying aliases.
   341  	instructions["B"] = arm64.AB
   342  	instructions["BL"] = arm64.ABL
   343  
   344  	return &Arch{
   345  		LinkArch:       &arm64.Linkarm64,
   346  		Instructions:   instructions,
   347  		Register:       register,
   348  		RegisterPrefix: registerPrefix,
   349  		RegisterNumber: arm64RegisterNumber,
   350  		IsJump:         jumpArm64,
   351  	}
   352  
   353  }
   354  
   355  func archPPC64(linkArch *obj.LinkArch) *Arch {
   356  	register := make(map[string]int16)
   357  	// Create maps for easy lookup of instruction names etc.
   358  	// Note that there is no list of names as there is for x86.
   359  	for i := ppc64.REG_R0; i <= ppc64.REG_R31; i++ {
   360  		register[obj.Rconv(i)] = int16(i)
   361  	}
   362  	for i := ppc64.REG_F0; i <= ppc64.REG_F31; i++ {
   363  		register[obj.Rconv(i)] = int16(i)
   364  	}
   365  	for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ {
   366  		register[obj.Rconv(i)] = int16(i)
   367  	}
   368  	for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ {
   369  		register[obj.Rconv(i)] = int16(i)
   370  	}
   371  	for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
   372  		register[obj.Rconv(i)] = int16(i)
   373  	}
   374  	for i := ppc64.REG_MSR; i <= ppc64.REG_CR; i++ {
   375  		register[obj.Rconv(i)] = int16(i)
   376  	}
   377  	register["CR"] = ppc64.REG_CR
   378  	register["XER"] = ppc64.REG_XER
   379  	register["LR"] = ppc64.REG_LR
   380  	register["CTR"] = ppc64.REG_CTR
   381  	register["FPSCR"] = ppc64.REG_FPSCR
   382  	register["MSR"] = ppc64.REG_MSR
   383  	// Pseudo-registers.
   384  	register["SB"] = RSB
   385  	register["FP"] = RFP
   386  	register["PC"] = RPC
   387  	// Avoid unintentionally clobbering g using R30.
   388  	delete(register, "R30")
   389  	register["g"] = ppc64.REG_R30
   390  	registerPrefix := map[string]bool{
   391  		"CR":  true,
   392  		"F":   true,
   393  		"R":   true,
   394  		"SPR": true,
   395  	}
   396  
   397  	instructions := make(map[string]obj.As)
   398  	for i, s := range obj.Anames {
   399  		instructions[s] = obj.As(i)
   400  	}
   401  	for i, s := range ppc64.Anames {
   402  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   403  			instructions[s] = obj.As(i) + obj.ABasePPC64
   404  		}
   405  	}
   406  	// Annoying aliases.
   407  	instructions["BR"] = ppc64.ABR
   408  	instructions["BL"] = ppc64.ABL
   409  
   410  	return &Arch{
   411  		LinkArch:       linkArch,
   412  		Instructions:   instructions,
   413  		Register:       register,
   414  		RegisterPrefix: registerPrefix,
   415  		RegisterNumber: ppc64RegisterNumber,
   416  		IsJump:         jumpPPC64,
   417  	}
   418  }
   419  
   420  func archMips(linkArch *obj.LinkArch) *Arch {
   421  	register := make(map[string]int16)
   422  	// Create maps for easy lookup of instruction names etc.
   423  	// Note that there is no list of names as there is for x86.
   424  	for i := mips.REG_R0; i <= mips.REG_R31; i++ {
   425  		register[obj.Rconv(i)] = int16(i)
   426  	}
   427  
   428  	for i := mips.REG_F0; i <= mips.REG_F31; i++ {
   429  		register[obj.Rconv(i)] = int16(i)
   430  	}
   431  	for i := mips.REG_M0; i <= mips.REG_M31; i++ {
   432  		register[obj.Rconv(i)] = int16(i)
   433  	}
   434  	for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
   435  		register[obj.Rconv(i)] = int16(i)
   436  	}
   437  	register["HI"] = mips.REG_HI
   438  	register["LO"] = mips.REG_LO
   439  	// Pseudo-registers.
   440  	register["SB"] = RSB
   441  	register["FP"] = RFP
   442  	register["PC"] = RPC
   443  	// Avoid unintentionally clobbering g using R30.
   444  	delete(register, "R30")
   445  	register["g"] = mips.REG_R30
   446  
   447  	registerPrefix := map[string]bool{
   448  		"F":   true,
   449  		"FCR": true,
   450  		"M":   true,
   451  		"R":   true,
   452  	}
   453  
   454  	instructions := make(map[string]obj.As)
   455  	for i, s := range obj.Anames {
   456  		instructions[s] = obj.As(i)
   457  	}
   458  	for i, s := range mips.Anames {
   459  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   460  			instructions[s] = obj.As(i) + obj.ABaseMIPS
   461  		}
   462  	}
   463  	// Annoying alias.
   464  	instructions["JAL"] = mips.AJAL
   465  
   466  	return &Arch{
   467  		LinkArch:       linkArch,
   468  		Instructions:   instructions,
   469  		Register:       register,
   470  		RegisterPrefix: registerPrefix,
   471  		RegisterNumber: mipsRegisterNumber,
   472  		IsJump:         jumpMIPS,
   473  	}
   474  }
   475  
   476  func archMips64(linkArch *obj.LinkArch) *Arch {
   477  	register := make(map[string]int16)
   478  	// Create maps for easy lookup of instruction names etc.
   479  	// Note that there is no list of names as there is for x86.
   480  	for i := mips.REG_R0; i <= mips.REG_R31; i++ {
   481  		register[obj.Rconv(i)] = int16(i)
   482  	}
   483  	for i := mips.REG_F0; i <= mips.REG_F31; i++ {
   484  		register[obj.Rconv(i)] = int16(i)
   485  	}
   486  	for i := mips.REG_M0; i <= mips.REG_M31; i++ {
   487  		register[obj.Rconv(i)] = int16(i)
   488  	}
   489  	for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
   490  		register[obj.Rconv(i)] = int16(i)
   491  	}
   492  	for i := mips.REG_W0; i <= mips.REG_W31; i++ {
   493  		register[obj.Rconv(i)] = int16(i)
   494  	}
   495  	register["HI"] = mips.REG_HI
   496  	register["LO"] = mips.REG_LO
   497  	// Pseudo-registers.
   498  	register["SB"] = RSB
   499  	register["FP"] = RFP
   500  	register["PC"] = RPC
   501  	// Avoid unintentionally clobbering g using R30.
   502  	delete(register, "R30")
   503  	register["g"] = mips.REG_R30
   504  	// Avoid unintentionally clobbering RSB using R28.
   505  	delete(register, "R28")
   506  	register["RSB"] = mips.REG_R28
   507  	registerPrefix := map[string]bool{
   508  		"F":   true,
   509  		"FCR": true,
   510  		"M":   true,
   511  		"R":   true,
   512  		"W":   true,
   513  	}
   514  
   515  	instructions := make(map[string]obj.As)
   516  	for i, s := range obj.Anames {
   517  		instructions[s] = obj.As(i)
   518  	}
   519  	for i, s := range mips.Anames {
   520  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   521  			instructions[s] = obj.As(i) + obj.ABaseMIPS
   522  		}
   523  	}
   524  	// Annoying alias.
   525  	instructions["JAL"] = mips.AJAL
   526  
   527  	return &Arch{
   528  		LinkArch:       linkArch,
   529  		Instructions:   instructions,
   530  		Register:       register,
   531  		RegisterPrefix: registerPrefix,
   532  		RegisterNumber: mipsRegisterNumber,
   533  		IsJump:         jumpMIPS,
   534  	}
   535  }
   536  
   537  func archRISCV64() *Arch {
   538  	register := make(map[string]int16)
   539  
   540  	// Standard register names.
   541  	for i := riscv.REG_X0; i <= riscv.REG_X31; i++ {
   542  		if i == riscv.REG_G {
   543  			continue
   544  		}
   545  		name := fmt.Sprintf("X%d", i-riscv.REG_X0)
   546  		register[name] = int16(i)
   547  	}
   548  	for i := riscv.REG_F0; i <= riscv.REG_F31; i++ {
   549  		name := fmt.Sprintf("F%d", i-riscv.REG_F0)
   550  		register[name] = int16(i)
   551  	}
   552  
   553  	// General registers with ABI names.
   554  	register["ZERO"] = riscv.REG_ZERO
   555  	register["RA"] = riscv.REG_RA
   556  	register["SP"] = riscv.REG_SP
   557  	register["GP"] = riscv.REG_GP
   558  	register["TP"] = riscv.REG_TP
   559  	register["T0"] = riscv.REG_T0
   560  	register["T1"] = riscv.REG_T1
   561  	register["T2"] = riscv.REG_T2
   562  	register["S0"] = riscv.REG_S0
   563  	register["S1"] = riscv.REG_S1
   564  	register["A0"] = riscv.REG_A0
   565  	register["A1"] = riscv.REG_A1
   566  	register["A2"] = riscv.REG_A2
   567  	register["A3"] = riscv.REG_A3
   568  	register["A4"] = riscv.REG_A4
   569  	register["A5"] = riscv.REG_A5
   570  	register["A6"] = riscv.REG_A6
   571  	register["A7"] = riscv.REG_A7
   572  	register["S2"] = riscv.REG_S2
   573  	register["S3"] = riscv.REG_S3
   574  	register["S4"] = riscv.REG_S4
   575  	register["S5"] = riscv.REG_S5
   576  	register["S6"] = riscv.REG_S6
   577  	register["S7"] = riscv.REG_S7
   578  	register["S8"] = riscv.REG_S8
   579  	register["S9"] = riscv.REG_S9
   580  	register["S10"] = riscv.REG_S10
   581  	// Skip S11 as it is the g register.
   582  	register["T3"] = riscv.REG_T3
   583  	register["T4"] = riscv.REG_T4
   584  	register["T5"] = riscv.REG_T5
   585  	register["T6"] = riscv.REG_T6
   586  
   587  	// Go runtime register names.
   588  	register["g"] = riscv.REG_G
   589  	register["CTXT"] = riscv.REG_CTXT
   590  	register["TMP"] = riscv.REG_TMP
   591  
   592  	// ABI names for floating point register.
   593  	register["FT0"] = riscv.REG_FT0
   594  	register["FT1"] = riscv.REG_FT1
   595  	register["FT2"] = riscv.REG_FT2
   596  	register["FT3"] = riscv.REG_FT3
   597  	register["FT4"] = riscv.REG_FT4
   598  	register["FT5"] = riscv.REG_FT5
   599  	register["FT6"] = riscv.REG_FT6
   600  	register["FT7"] = riscv.REG_FT7
   601  	register["FS0"] = riscv.REG_FS0
   602  	register["FS1"] = riscv.REG_FS1
   603  	register["FA0"] = riscv.REG_FA0
   604  	register["FA1"] = riscv.REG_FA1
   605  	register["FA2"] = riscv.REG_FA2
   606  	register["FA3"] = riscv.REG_FA3
   607  	register["FA4"] = riscv.REG_FA4
   608  	register["FA5"] = riscv.REG_FA5
   609  	register["FA6"] = riscv.REG_FA6
   610  	register["FA7"] = riscv.REG_FA7
   611  	register["FS2"] = riscv.REG_FS2
   612  	register["FS3"] = riscv.REG_FS3
   613  	register["FS4"] = riscv.REG_FS4
   614  	register["FS5"] = riscv.REG_FS5
   615  	register["FS6"] = riscv.REG_FS6
   616  	register["FS7"] = riscv.REG_FS7
   617  	register["FS8"] = riscv.REG_FS8
   618  	register["FS9"] = riscv.REG_FS9
   619  	register["FS10"] = riscv.REG_FS10
   620  	register["FS11"] = riscv.REG_FS11
   621  	register["FT8"] = riscv.REG_FT8
   622  	register["FT9"] = riscv.REG_FT9
   623  	register["FT10"] = riscv.REG_FT10
   624  	register["FT11"] = riscv.REG_FT11
   625  
   626  	// Pseudo-registers.
   627  	register["SB"] = RSB
   628  	register["FP"] = RFP
   629  	register["PC"] = RPC
   630  
   631  	instructions := make(map[string]obj.As)
   632  	for i, s := range obj.Anames {
   633  		instructions[s] = obj.As(i)
   634  	}
   635  	for i, s := range riscv.Anames {
   636  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   637  			instructions[s] = obj.As(i) + obj.ABaseRISCV
   638  		}
   639  	}
   640  
   641  	return &Arch{
   642  		LinkArch:       &riscv.LinkRISCV64,
   643  		Instructions:   instructions,
   644  		Register:       register,
   645  		RegisterPrefix: nil,
   646  		RegisterNumber: nilRegisterNumber,
   647  		IsJump:         jumpRISCV,
   648  	}
   649  }
   650  
   651  func archS390x() *Arch {
   652  	register := make(map[string]int16)
   653  	// Create maps for easy lookup of instruction names etc.
   654  	// Note that there is no list of names as there is for x86.
   655  	for i := s390x.REG_R0; i <= s390x.REG_R15; i++ {
   656  		register[obj.Rconv(i)] = int16(i)
   657  	}
   658  	for i := s390x.REG_F0; i <= s390x.REG_F15; i++ {
   659  		register[obj.Rconv(i)] = int16(i)
   660  	}
   661  	for i := s390x.REG_V0; i <= s390x.REG_V31; i++ {
   662  		register[obj.Rconv(i)] = int16(i)
   663  	}
   664  	for i := s390x.REG_AR0; i <= s390x.REG_AR15; i++ {
   665  		register[obj.Rconv(i)] = int16(i)
   666  	}
   667  	register["LR"] = s390x.REG_LR
   668  	// Pseudo-registers.
   669  	register["SB"] = RSB
   670  	register["FP"] = RFP
   671  	register["PC"] = RPC
   672  	// Avoid unintentionally clobbering g using R13.
   673  	delete(register, "R13")
   674  	register["g"] = s390x.REG_R13
   675  	registerPrefix := map[string]bool{
   676  		"AR": true,
   677  		"F":  true,
   678  		"R":  true,
   679  	}
   680  
   681  	instructions := make(map[string]obj.As)
   682  	for i, s := range obj.Anames {
   683  		instructions[s] = obj.As(i)
   684  	}
   685  	for i, s := range s390x.Anames {
   686  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   687  			instructions[s] = obj.As(i) + obj.ABaseS390X
   688  		}
   689  	}
   690  	// Annoying aliases.
   691  	instructions["BR"] = s390x.ABR
   692  	instructions["BL"] = s390x.ABL
   693  
   694  	return &Arch{
   695  		LinkArch:       &s390x.Links390x,
   696  		Instructions:   instructions,
   697  		Register:       register,
   698  		RegisterPrefix: registerPrefix,
   699  		RegisterNumber: s390xRegisterNumber,
   700  		IsJump:         jumpS390x,
   701  	}
   702  }
   703  
   704  func archWasm() *Arch {
   705  	instructions := make(map[string]obj.As)
   706  	for i, s := range obj.Anames {
   707  		instructions[s] = obj.As(i)
   708  	}
   709  	for i, s := range wasm.Anames {
   710  		if obj.As(i) >= obj.A_ARCHSPECIFIC {
   711  			instructions[s] = obj.As(i) + obj.ABaseWasm
   712  		}
   713  	}
   714  
   715  	return &Arch{
   716  		LinkArch:       &wasm.Linkwasm,
   717  		Instructions:   instructions,
   718  		Register:       wasm.Register,
   719  		RegisterPrefix: nil,
   720  		RegisterNumber: nilRegisterNumber,
   721  		IsJump:         jumpWasm,
   722  	}
   723  }
   724
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