Source file src/cmd/internal/obj/arm64/a.out.go

Documentation: cmd/internal/obj/arm64

     1  // cmd/7c/7.out.h  from Vita Nuova.
     2  // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h
     3  //
     4  // 	Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
     5  // 	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     6  // 	Portions Copyright © 1997-1999 Vita Nuova Limited
     7  // 	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
     8  // 	Portions Copyright © 2004,2006 Bruce Ellis
     9  // 	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
    10  // 	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
    11  // 	Portions Copyright © 2009 The Go Authors. All rights reserved.
    12  //
    13  // Permission is hereby granted, free of charge, to any person obtaining a copy
    14  // of this software and associated documentation files (the "Software"), to deal
    15  // in the Software without restriction, including without limitation the rights
    16  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    17  // copies of the Software, and to permit persons to whom the Software is
    18  // furnished to do so, subject to the following conditions:
    19  //
    20  // The above copyright notice and this permission notice shall be included in
    21  // all copies or substantial portions of the Software.
    22  //
    23  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    24  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    25  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    26  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    27  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    28  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    29  // THE SOFTWARE.
    30  
    31  package arm64
    32  
    33  import "cmd/internal/obj"
    34  
    35  const (
    36  	NSNAME = 8
    37  	NSYM   = 50
    38  	NREG   = 32 /* number of general registers */
    39  	NFREG  = 32 /* number of floating point registers */
    40  )
    41  
    42  // General purpose registers, kept in the low bits of Prog.Reg.
    43  const (
    44  	// integer
    45  	REG_R0 = obj.RBaseARM64 + iota
    46  	REG_R1
    47  	REG_R2
    48  	REG_R3
    49  	REG_R4
    50  	REG_R5
    51  	REG_R6
    52  	REG_R7
    53  	REG_R8
    54  	REG_R9
    55  	REG_R10
    56  	REG_R11
    57  	REG_R12
    58  	REG_R13
    59  	REG_R14
    60  	REG_R15
    61  	REG_R16
    62  	REG_R17
    63  	REG_R18
    64  	REG_R19
    65  	REG_R20
    66  	REG_R21
    67  	REG_R22
    68  	REG_R23
    69  	REG_R24
    70  	REG_R25
    71  	REG_R26
    72  	REG_R27
    73  	REG_R28
    74  	REG_R29
    75  	REG_R30
    76  	REG_R31
    77  
    78  	// scalar floating point
    79  	REG_F0
    80  	REG_F1
    81  	REG_F2
    82  	REG_F3
    83  	REG_F4
    84  	REG_F5
    85  	REG_F6
    86  	REG_F7
    87  	REG_F8
    88  	REG_F9
    89  	REG_F10
    90  	REG_F11
    91  	REG_F12
    92  	REG_F13
    93  	REG_F14
    94  	REG_F15
    95  	REG_F16
    96  	REG_F17
    97  	REG_F18
    98  	REG_F19
    99  	REG_F20
   100  	REG_F21
   101  	REG_F22
   102  	REG_F23
   103  	REG_F24
   104  	REG_F25
   105  	REG_F26
   106  	REG_F27
   107  	REG_F28
   108  	REG_F29
   109  	REG_F30
   110  	REG_F31
   111  
   112  	// SIMD
   113  	REG_V0
   114  	REG_V1
   115  	REG_V2
   116  	REG_V3
   117  	REG_V4
   118  	REG_V5
   119  	REG_V6
   120  	REG_V7
   121  	REG_V8
   122  	REG_V9
   123  	REG_V10
   124  	REG_V11
   125  	REG_V12
   126  	REG_V13
   127  	REG_V14
   128  	REG_V15
   129  	REG_V16
   130  	REG_V17
   131  	REG_V18
   132  	REG_V19
   133  	REG_V20
   134  	REG_V21
   135  	REG_V22
   136  	REG_V23
   137  	REG_V24
   138  	REG_V25
   139  	REG_V26
   140  	REG_V27
   141  	REG_V28
   142  	REG_V29
   143  	REG_V30
   144  	REG_V31
   145  
   146  	// The EQ in
   147  	// 	CSET	EQ, R0
   148  	// is encoded as TYPE_REG, even though it's not really a register.
   149  	COND_EQ
   150  	COND_NE
   151  	COND_HS
   152  	COND_LO
   153  	COND_MI
   154  	COND_PL
   155  	COND_VS
   156  	COND_VC
   157  	COND_HI
   158  	COND_LS
   159  	COND_GE
   160  	COND_LT
   161  	COND_GT
   162  	COND_LE
   163  	COND_AL
   164  	COND_NV
   165  
   166  	REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
   167  )
   168  
   169  // bits 0-4 indicates register: Vn
   170  // bits 5-8 indicates arrangement: <T>
   171  const (
   172  	REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
   173  	REG_ELEM                                    // Vn.<T>[index]
   174  	REG_ELEM_END
   175  )
   176  
   177  // Not registers, but flags that can be combined with regular register
   178  // constants to indicate extended register conversion. When checking,
   179  // you should subtract obj.RBaseARM64 first. From this difference, bit 11
   180  // indicates extended register, bits 8-10 select the conversion mode.
   181  // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
   182  const REG_LSL = obj.RBaseARM64 + 1<<9
   183  const REG_EXT = obj.RBaseARM64 + 1<<11
   184  
   185  const (
   186  	REG_UXTB = REG_EXT + iota<<8
   187  	REG_UXTH
   188  	REG_UXTW
   189  	REG_UXTX
   190  	REG_SXTB
   191  	REG_SXTH
   192  	REG_SXTW
   193  	REG_SXTX
   194  )
   195  
   196  // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
   197  // a special register and the low bits select the register.
   198  // SYSREG_END is the last item in the automatically generated system register
   199  // declaration, and it is defined in the sysRegEnc.go file.
   200  const (
   201  	REG_SPECIAL = obj.RBaseARM64 + 1<<12
   202  	REG_DAIFSet = SYSREG_END + iota
   203  	REG_DAIFClr
   204  	REG_PLDL1KEEP
   205  	REG_PLDL1STRM
   206  	REG_PLDL2KEEP
   207  	REG_PLDL2STRM
   208  	REG_PLDL3KEEP
   209  	REG_PLDL3STRM
   210  	REG_PLIL1KEEP
   211  	REG_PLIL1STRM
   212  	REG_PLIL2KEEP
   213  	REG_PLIL2STRM
   214  	REG_PLIL3KEEP
   215  	REG_PLIL3STRM
   216  	REG_PSTL1KEEP
   217  	REG_PSTL1STRM
   218  	REG_PSTL2KEEP
   219  	REG_PSTL2STRM
   220  	REG_PSTL3KEEP
   221  	REG_PSTL3STRM
   222  )
   223  
   224  // Register assignments:
   225  //
   226  // compiler allocates R0 up as temps
   227  // compiler allocates register variables R7-R25
   228  // compiler allocates external registers R26 down
   229  //
   230  // compiler allocates register variables F7-F26
   231  // compiler allocates external registers F26 down
   232  const (
   233  	REGMIN = REG_R7  // register variables allocated from here to REGMAX
   234  	REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline
   235  	REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline
   236  	REGPR  = REG_R18 // ARM64 platform register, unused in the Go toolchain
   237  	REGMAX = REG_R25
   238  
   239  	REGCTXT = REG_R26 // environment for closures
   240  	REGTMP  = REG_R27 // reserved for liblink
   241  	REGG    = REG_R28 // G
   242  	REGFP   = REG_R29 // frame pointer
   243  	REGLINK = REG_R30
   244  
   245  	// ARM64 uses R31 as both stack pointer and zero register,
   246  	// depending on the instruction. To differentiate RSP from ZR,
   247  	// we use a different numeric value for REGZERO and REGSP.
   248  	REGZERO = REG_R31
   249  	REGSP   = REG_RSP
   250  
   251  	FREGRET = REG_F0
   252  	FREGMIN = REG_F7  // first register variable
   253  	FREGMAX = REG_F26 // last register variable for 7g only
   254  	FREGEXT = REG_F26 // first external register
   255  )
   256  
   257  // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf
   258  var ARM64DWARFRegisters = map[int16]int16{
   259  	REG_R0:  0,
   260  	REG_R1:  1,
   261  	REG_R2:  2,
   262  	REG_R3:  3,
   263  	REG_R4:  4,
   264  	REG_R5:  5,
   265  	REG_R6:  6,
   266  	REG_R7:  7,
   267  	REG_R8:  8,
   268  	REG_R9:  9,
   269  	REG_R10: 10,
   270  	REG_R11: 11,
   271  	REG_R12: 12,
   272  	REG_R13: 13,
   273  	REG_R14: 14,
   274  	REG_R15: 15,
   275  	REG_R16: 16,
   276  	REG_R17: 17,
   277  	REG_R18: 18,
   278  	REG_R19: 19,
   279  	REG_R20: 20,
   280  	REG_R21: 21,
   281  	REG_R22: 22,
   282  	REG_R23: 23,
   283  	REG_R24: 24,
   284  	REG_R25: 25,
   285  	REG_R26: 26,
   286  	REG_R27: 27,
   287  	REG_R28: 28,
   288  	REG_R29: 29,
   289  	REG_R30: 30,
   290  
   291  	// floating point
   292  	REG_F0:  64,
   293  	REG_F1:  65,
   294  	REG_F2:  66,
   295  	REG_F3:  67,
   296  	REG_F4:  68,
   297  	REG_F5:  69,
   298  	REG_F6:  70,
   299  	REG_F7:  71,
   300  	REG_F8:  72,
   301  	REG_F9:  73,
   302  	REG_F10: 74,
   303  	REG_F11: 75,
   304  	REG_F12: 76,
   305  	REG_F13: 77,
   306  	REG_F14: 78,
   307  	REG_F15: 79,
   308  	REG_F16: 80,
   309  	REG_F17: 81,
   310  	REG_F18: 82,
   311  	REG_F19: 83,
   312  	REG_F20: 84,
   313  	REG_F21: 85,
   314  	REG_F22: 86,
   315  	REG_F23: 87,
   316  	REG_F24: 88,
   317  	REG_F25: 89,
   318  	REG_F26: 90,
   319  	REG_F27: 91,
   320  	REG_F28: 92,
   321  	REG_F29: 93,
   322  	REG_F30: 94,
   323  	REG_F31: 95,
   324  
   325  	// SIMD
   326  	REG_V0:  64,
   327  	REG_V1:  65,
   328  	REG_V2:  66,
   329  	REG_V3:  67,
   330  	REG_V4:  68,
   331  	REG_V5:  69,
   332  	REG_V6:  70,
   333  	REG_V7:  71,
   334  	REG_V8:  72,
   335  	REG_V9:  73,
   336  	REG_V10: 74,
   337  	REG_V11: 75,
   338  	REG_V12: 76,
   339  	REG_V13: 77,
   340  	REG_V14: 78,
   341  	REG_V15: 79,
   342  	REG_V16: 80,
   343  	REG_V17: 81,
   344  	REG_V18: 82,
   345  	REG_V19: 83,
   346  	REG_V20: 84,
   347  	REG_V21: 85,
   348  	REG_V22: 86,
   349  	REG_V23: 87,
   350  	REG_V24: 88,
   351  	REG_V25: 89,
   352  	REG_V26: 90,
   353  	REG_V27: 91,
   354  	REG_V28: 92,
   355  	REG_V29: 93,
   356  	REG_V30: 94,
   357  	REG_V31: 95,
   358  }
   359  
   360  const (
   361  	BIG = 2048 - 8
   362  )
   363  
   364  const (
   365  	/* mark flags */
   366  	LABEL = 1 << iota
   367  	LEAF
   368  	FLOAT
   369  	BRANCH
   370  	LOAD
   371  	FCMP
   372  	SYNC
   373  	LIST
   374  	FOLL
   375  	NOSCHED
   376  )
   377  
   378  const (
   379  	// optab is sorted based on the order of these constants
   380  	// and the first match is chosen.
   381  	// The more specific class needs to come earlier.
   382  	C_NONE   = iota
   383  	C_REG    // R0..R30
   384  	C_RSP    // R0..R30, RSP
   385  	C_FREG   // F0..F31
   386  	C_VREG   // V0..V31
   387  	C_PAIR   // (Rn, Rm)
   388  	C_SHIFT  // Rn<<2
   389  	C_EXTREG // Rn.UXTB[<<3]
   390  	C_SPR    // REG_NZCV
   391  	C_COND   // EQ, NE, etc
   392  	C_ARNG   // Vn.<T>
   393  	C_ELEM   // Vn.<T>[index]
   394  	C_LIST   // [V1, V2, V3]
   395  
   396  	C_ZCON     // $0 or ZR
   397  	C_ABCON0   // could be C_ADDCON0 or C_BITCON
   398  	C_ADDCON0  // 12-bit unsigned, unshifted
   399  	C_ABCON    // could be C_ADDCON or C_BITCON
   400  	C_AMCON    // could be C_ADDCON or C_MOVCON
   401  	C_ADDCON   // 12-bit unsigned, shifted left by 0 or 12
   402  	C_MBCON    // could be C_MOVCON or C_BITCON
   403  	C_MOVCON   // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
   404  	C_BITCON   // bitfield and logical immediate masks
   405  	C_ADDCON2  // 24-bit constant
   406  	C_LCON     // 32-bit constant
   407  	C_MOVCON2  // a constant that can be loaded with one MOVZ/MOVN and one MOVK
   408  	C_MOVCON3  // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
   409  	C_VCON     // 64-bit constant
   410  	C_FCON     // floating-point constant
   411  	C_VCONADDR // 64-bit memory address
   412  
   413  	C_AACON  // ADDCON offset in auto constant $a(FP)
   414  	C_AACON2 // 24-bit offset in auto constant $a(FP)
   415  	C_LACON  // 32-bit offset in auto constant $a(FP)
   416  	C_AECON  // ADDCON offset in extern constant $e(SB)
   417  
   418  	// TODO(aram): only one branch class should be enough
   419  	C_SBRA // for TYPE_BRANCH
   420  	C_LBRA
   421  
   422  	C_ZAUTO       // 0(RSP)
   423  	C_NSAUTO_16   // -256 <= x < 0, 0 mod 16
   424  	C_NSAUTO_8    // -256 <= x < 0, 0 mod 8
   425  	C_NSAUTO_4    // -256 <= x < 0, 0 mod 4
   426  	C_NSAUTO      // -256 <= x < 0
   427  	C_NPAUTO_16   // -512 <= x < 0, 0 mod 16
   428  	C_NPAUTO      // -512 <= x < 0, 0 mod 8
   429  	C_NQAUTO_16   // -1024 <= x < 0, 0 mod 16
   430  	C_NAUTO4K     // -4095 <= x < 0
   431  	C_PSAUTO_16   // 0 to 255, 0 mod 16
   432  	C_PSAUTO_8    // 0 to 255, 0 mod 8
   433  	C_PSAUTO_4    // 0 to 255, 0 mod 4
   434  	C_PSAUTO      // 0 to 255
   435  	C_PPAUTO_16   // 0 to 504, 0 mod 16
   436  	C_PPAUTO      // 0 to 504, 0 mod 8
   437  	C_PQAUTO_16   // 0 to 1008, 0 mod 16
   438  	C_UAUTO4K_16  // 0 to 4095, 0 mod 16
   439  	C_UAUTO4K_8   // 0 to 4095, 0 mod 8
   440  	C_UAUTO4K_4   // 0 to 4095, 0 mod 4
   441  	C_UAUTO4K_2   // 0 to 4095, 0 mod 2
   442  	C_UAUTO4K     // 0 to 4095
   443  	C_UAUTO8K_16  // 0 to 8190, 0 mod 16
   444  	C_UAUTO8K_8   // 0 to 8190, 0 mod 8
   445  	C_UAUTO8K_4   // 0 to 8190, 0 mod 4
   446  	C_UAUTO8K     // 0 to 8190, 0 mod 2  + C_PSAUTO
   447  	C_UAUTO16K_16 // 0 to 16380, 0 mod 16
   448  	C_UAUTO16K_8  // 0 to 16380, 0 mod 8
   449  	C_UAUTO16K    // 0 to 16380, 0 mod 4 + C_PSAUTO
   450  	C_UAUTO32K_16 // 0 to 32760, 0 mod 16 + C_PSAUTO
   451  	C_UAUTO32K    // 0 to 32760, 0 mod 8 + C_PSAUTO
   452  	C_UAUTO64K    // 0 to 65520, 0 mod 16 + C_PSAUTO
   453  	C_LAUTO       // any other 32-bit constant
   454  
   455  	C_SEXT1  // 0 to 4095, direct
   456  	C_SEXT2  // 0 to 8190
   457  	C_SEXT4  // 0 to 16380
   458  	C_SEXT8  // 0 to 32760
   459  	C_SEXT16 // 0 to 65520
   460  	C_LEXT
   461  
   462  	C_ZOREG     // 0(R)
   463  	C_NSOREG_16 // must mirror C_NSAUTO_16, etc
   464  	C_NSOREG_8
   465  	C_NSOREG_4
   466  	C_NSOREG
   467  	C_NPOREG_16
   468  	C_NPOREG
   469  	C_NQOREG_16
   470  	C_NOREG4K
   471  	C_PSOREG_16
   472  	C_PSOREG_8
   473  	C_PSOREG_4
   474  	C_PSOREG
   475  	C_PPOREG_16
   476  	C_PPOREG
   477  	C_PQOREG_16
   478  	C_UOREG4K_16
   479  	C_UOREG4K_8
   480  	C_UOREG4K_4
   481  	C_UOREG4K_2
   482  	C_UOREG4K
   483  	C_UOREG8K_16
   484  	C_UOREG8K_8
   485  	C_UOREG8K_4
   486  	C_UOREG8K
   487  	C_UOREG16K_16
   488  	C_UOREG16K_8
   489  	C_UOREG16K
   490  	C_UOREG32K_16
   491  	C_UOREG32K
   492  	C_UOREG64K
   493  	C_LOREG
   494  
   495  	C_ADDR // TODO(aram): explain difference from C_VCONADDR
   496  
   497  	// The GOT slot for a symbol in -dynlink mode.
   498  	C_GOTADDR
   499  
   500  	// TLS "var" in local exec mode: will become a constant offset from
   501  	// thread local base that is ultimately chosen by the program linker.
   502  	C_TLS_LE
   503  
   504  	// TLS "var" in initial exec mode: will become a memory address (chosen
   505  	// by the program linker) that the dynamic linker will fill with the
   506  	// offset from the thread local base.
   507  	C_TLS_IE
   508  
   509  	C_ROFF // register offset (including register extended)
   510  
   511  	C_GOK
   512  	C_TEXTSIZE
   513  	C_NCLASS // must be last
   514  )
   515  
   516  const (
   517  	C_XPRE  = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
   518  	C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
   519  )
   520  
   521  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
   522  
   523  const (
   524  	AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
   525  	AADCS
   526  	AADCSW
   527  	AADCW
   528  	AADD
   529  	AADDS
   530  	AADDSW
   531  	AADDW
   532  	AADR
   533  	AADRP
   534  	AAND
   535  	AANDS
   536  	AANDSW
   537  	AANDW
   538  	AASR
   539  	AASRW
   540  	AAT
   541  	ABFI
   542  	ABFIW
   543  	ABFM
   544  	ABFMW
   545  	ABFXIL
   546  	ABFXILW
   547  	ABIC
   548  	ABICS
   549  	ABICSW
   550  	ABICW
   551  	ABRK
   552  	ACBNZ
   553  	ACBNZW
   554  	ACBZ
   555  	ACBZW
   556  	ACCMN
   557  	ACCMNW
   558  	ACCMP
   559  	ACCMPW
   560  	ACINC
   561  	ACINCW
   562  	ACINV
   563  	ACINVW
   564  	ACLREX
   565  	ACLS
   566  	ACLSW
   567  	ACLZ
   568  	ACLZW
   569  	ACMN
   570  	ACMNW
   571  	ACMP
   572  	ACMPW
   573  	ACNEG
   574  	ACNEGW
   575  	ACRC32B
   576  	ACRC32CB
   577  	ACRC32CH
   578  	ACRC32CW
   579  	ACRC32CX
   580  	ACRC32H
   581  	ACRC32W
   582  	ACRC32X
   583  	ACSEL
   584  	ACSELW
   585  	ACSET
   586  	ACSETM
   587  	ACSETMW
   588  	ACSETW
   589  	ACSINC
   590  	ACSINCW
   591  	ACSINV
   592  	ACSINVW
   593  	ACSNEG
   594  	ACSNEGW
   595  	ADC
   596  	ADCPS1
   597  	ADCPS2
   598  	ADCPS3
   599  	ADMB
   600  	ADRPS
   601  	ADSB
   602  	AEON
   603  	AEONW
   604  	AEOR
   605  	AEORW
   606  	AERET
   607  	AEXTR
   608  	AEXTRW
   609  	AHINT
   610  	AHLT
   611  	AHVC
   612  	AIC
   613  	AISB
   614  	ALDADDAB
   615  	ALDADDAD
   616  	ALDADDAH
   617  	ALDADDAW
   618  	ALDADDALB
   619  	ALDADDALD
   620  	ALDADDALH
   621  	ALDADDALW
   622  	ALDADDB
   623  	ALDADDD
   624  	ALDADDH
   625  	ALDADDW
   626  	ALDADDLB
   627  	ALDADDLD
   628  	ALDADDLH
   629  	ALDADDLW
   630  	ALDAR
   631  	ALDARB
   632  	ALDARH
   633  	ALDARW
   634  	ALDAXP
   635  	ALDAXPW
   636  	ALDAXR
   637  	ALDAXRB
   638  	ALDAXRH
   639  	ALDAXRW
   640  	ALDCLRAB
   641  	ALDCLRAD
   642  	ALDCLRAH
   643  	ALDCLRAW
   644  	ALDCLRALB
   645  	ALDCLRALD
   646  	ALDCLRALH
   647  	ALDCLRALW
   648  	ALDCLRB
   649  	ALDCLRD
   650  	ALDCLRH
   651  	ALDCLRW
   652  	ALDCLRLB
   653  	ALDCLRLD
   654  	ALDCLRLH
   655  	ALDCLRLW
   656  	ALDEORAB
   657  	ALDEORAD
   658  	ALDEORAH
   659  	ALDEORAW
   660  	ALDEORALB
   661  	ALDEORALD
   662  	ALDEORALH
   663  	ALDEORALW
   664  	ALDEORB
   665  	ALDEORD
   666  	ALDEORH
   667  	ALDEORW
   668  	ALDEORLB
   669  	ALDEORLD
   670  	ALDEORLH
   671  	ALDEORLW
   672  	ALDORAB
   673  	ALDORAD
   674  	ALDORAH
   675  	ALDORAW
   676  	ALDORALB
   677  	ALDORALD
   678  	ALDORALH
   679  	ALDORALW
   680  	ALDORB
   681  	ALDORD
   682  	ALDORH
   683  	ALDORW
   684  	ALDORLB
   685  	ALDORLD
   686  	ALDORLH
   687  	ALDORLW
   688  	ALDP
   689  	ALDPW
   690  	ALDPSW
   691  	ALDXR
   692  	ALDXRB
   693  	ALDXRH
   694  	ALDXRW
   695  	ALDXP
   696  	ALDXPW
   697  	ALSL
   698  	ALSLW
   699  	ALSR
   700  	ALSRW
   701  	AMADD
   702  	AMADDW
   703  	AMNEG
   704  	AMNEGW
   705  	AMOVK
   706  	AMOVKW
   707  	AMOVN
   708  	AMOVNW
   709  	AMOVZ
   710  	AMOVZW
   711  	AMRS
   712  	AMSR
   713  	AMSUB
   714  	AMSUBW
   715  	AMUL
   716  	AMULW
   717  	AMVN
   718  	AMVNW
   719  	ANEG
   720  	ANEGS
   721  	ANEGSW
   722  	ANEGW
   723  	ANGC
   724  	ANGCS
   725  	ANGCSW
   726  	ANGCW
   727  	ANOOP
   728  	AORN
   729  	AORNW
   730  	AORR
   731  	AORRW
   732  	APRFM
   733  	APRFUM
   734  	ARBIT
   735  	ARBITW
   736  	AREM
   737  	AREMW
   738  	AREV
   739  	AREV16
   740  	AREV16W
   741  	AREV32
   742  	AREVW
   743  	AROR
   744  	ARORW
   745  	ASBC
   746  	ASBCS
   747  	ASBCSW
   748  	ASBCW
   749  	ASBFIZ
   750  	ASBFIZW
   751  	ASBFM
   752  	ASBFMW
   753  	ASBFX
   754  	ASBFXW
   755  	ASDIV
   756  	ASDIVW
   757  	ASEV
   758  	ASEVL
   759  	ASMADDL
   760  	ASMC
   761  	ASMNEGL
   762  	ASMSUBL
   763  	ASMULH
   764  	ASMULL
   765  	ASTXR
   766  	ASTXRB
   767  	ASTXRH
   768  	ASTXP
   769  	ASTXPW
   770  	ASTXRW
   771  	ASTLP
   772  	ASTLPW
   773  	ASTLR
   774  	ASTLRB
   775  	ASTLRH
   776  	ASTLRW
   777  	ASTLXP
   778  	ASTLXPW
   779  	ASTLXR
   780  	ASTLXRB
   781  	ASTLXRH
   782  	ASTLXRW
   783  	ASTP
   784  	ASTPW
   785  	ASUB
   786  	ASUBS
   787  	ASUBSW
   788  	ASUBW
   789  	ASVC
   790  	ASXTB
   791  	ASXTBW
   792  	ASXTH
   793  	ASXTHW
   794  	ASXTW
   795  	ASYS
   796  	ASYSL
   797  	ATBNZ
   798  	ATBZ
   799  	ATLBI
   800  	ATST
   801  	ATSTW
   802  	AUBFIZ
   803  	AUBFIZW
   804  	AUBFM
   805  	AUBFMW
   806  	AUBFX
   807  	AUBFXW
   808  	AUDIV
   809  	AUDIVW
   810  	AUMADDL
   811  	AUMNEGL
   812  	AUMSUBL
   813  	AUMULH
   814  	AUMULL
   815  	AUREM
   816  	AUREMW
   817  	AUXTB
   818  	AUXTH
   819  	AUXTW
   820  	AUXTBW
   821  	AUXTHW
   822  	AWFE
   823  	AWFI
   824  	AYIELD
   825  	AMOVB
   826  	AMOVBU
   827  	AMOVH
   828  	AMOVHU
   829  	AMOVW
   830  	AMOVWU
   831  	AMOVD
   832  	AMOVNP
   833  	AMOVNPW
   834  	AMOVP
   835  	AMOVPD
   836  	AMOVPQ
   837  	AMOVPS
   838  	AMOVPSW
   839  	AMOVPW
   840  	ASWPAD
   841  	ASWPAW
   842  	ASWPAH
   843  	ASWPAB
   844  	ASWPALD
   845  	ASWPALW
   846  	ASWPALH
   847  	ASWPALB
   848  	ASWPD
   849  	ASWPW
   850  	ASWPH
   851  	ASWPB
   852  	ASWPLD
   853  	ASWPLW
   854  	ASWPLH
   855  	ASWPLB
   856  	ACASD
   857  	ACASW
   858  	ACASH
   859  	ACASB
   860  	ACASAD
   861  	ACASAW
   862  	ACASLD
   863  	ACASLW
   864  	ACASALD
   865  	ACASALW
   866  	ACASALH
   867  	ACASALB
   868  	ACASPD
   869  	ACASPW
   870  	ABEQ
   871  	ABNE
   872  	ABCS
   873  	ABHS
   874  	ABCC
   875  	ABLO
   876  	ABMI
   877  	ABPL
   878  	ABVS
   879  	ABVC
   880  	ABHI
   881  	ABLS
   882  	ABGE
   883  	ABLT
   884  	ABGT
   885  	ABLE
   886  	AFABSD
   887  	AFABSS
   888  	AFADDD
   889  	AFADDS
   890  	AFCCMPD
   891  	AFCCMPED
   892  	AFCCMPS
   893  	AFCCMPES
   894  	AFCMPD
   895  	AFCMPED
   896  	AFCMPES
   897  	AFCMPS
   898  	AFCVTSD
   899  	AFCVTDS
   900  	AFCVTZSD
   901  	AFCVTZSDW
   902  	AFCVTZSS
   903  	AFCVTZSSW
   904  	AFCVTZUD
   905  	AFCVTZUDW
   906  	AFCVTZUS
   907  	AFCVTZUSW
   908  	AFDIVD
   909  	AFDIVS
   910  	AFLDPD
   911  	AFLDPQ
   912  	AFLDPS
   913  	AFMOVQ
   914  	AFMOVD
   915  	AFMOVS
   916  	AVMOVQ
   917  	AVMOVD
   918  	AVMOVS
   919  	AFMULD
   920  	AFMULS
   921  	AFNEGD
   922  	AFNEGS
   923  	AFSQRTD
   924  	AFSQRTS
   925  	AFSTPD
   926  	AFSTPQ
   927  	AFSTPS
   928  	AFSUBD
   929  	AFSUBS
   930  	ASCVTFD
   931  	ASCVTFS
   932  	ASCVTFWD
   933  	ASCVTFWS
   934  	AUCVTFD
   935  	AUCVTFS
   936  	AUCVTFWD
   937  	AUCVTFWS
   938  	AWORD
   939  	ADWORD
   940  	AFCSELS
   941  	AFCSELD
   942  	AFMAXS
   943  	AFMINS
   944  	AFMAXD
   945  	AFMIND
   946  	AFMAXNMS
   947  	AFMAXNMD
   948  	AFNMULS
   949  	AFNMULD
   950  	AFRINTNS
   951  	AFRINTND
   952  	AFRINTPS
   953  	AFRINTPD
   954  	AFRINTMS
   955  	AFRINTMD
   956  	AFRINTZS
   957  	AFRINTZD
   958  	AFRINTAS
   959  	AFRINTAD
   960  	AFRINTXS
   961  	AFRINTXD
   962  	AFRINTIS
   963  	AFRINTID
   964  	AFMADDS
   965  	AFMADDD
   966  	AFMSUBS
   967  	AFMSUBD
   968  	AFNMADDS
   969  	AFNMADDD
   970  	AFNMSUBS
   971  	AFNMSUBD
   972  	AFMINNMS
   973  	AFMINNMD
   974  	AFCVTDH
   975  	AFCVTHS
   976  	AFCVTHD
   977  	AFCVTSH
   978  	AAESD
   979  	AAESE
   980  	AAESIMC
   981  	AAESMC
   982  	ASHA1C
   983  	ASHA1H
   984  	ASHA1M
   985  	ASHA1P
   986  	ASHA1SU0
   987  	ASHA1SU1
   988  	ASHA256H
   989  	ASHA256H2
   990  	ASHA256SU0
   991  	ASHA256SU1
   992  	ASHA512H
   993  	ASHA512H2
   994  	ASHA512SU0
   995  	ASHA512SU1
   996  	AVADD
   997  	AVADDP
   998  	AVAND
   999  	AVBIF
  1000  	AVBCAX
  1001  	AVCMEQ
  1002  	AVCNT
  1003  	AVEOR
  1004  	AVEOR3
  1005  	AVMOV
  1006  	AVLD1
  1007  	AVLD2
  1008  	AVLD3
  1009  	AVLD4
  1010  	AVLD1R
  1011  	AVLD2R
  1012  	AVLD3R
  1013  	AVLD4R
  1014  	AVORR
  1015  	AVREV16
  1016  	AVREV32
  1017  	AVREV64
  1018  	AVST1
  1019  	AVST2
  1020  	AVST3
  1021  	AVST4
  1022  	AVDUP
  1023  	AVADDV
  1024  	AVMOVI
  1025  	AVUADDLV
  1026  	AVSUB
  1027  	AVFMLA
  1028  	AVFMLS
  1029  	AVPMULL
  1030  	AVPMULL2
  1031  	AVEXT
  1032  	AVRBIT
  1033  	AVRAX1
  1034  	AVUMAX
  1035  	AVUMIN
  1036  	AVUSHR
  1037  	AVUSHLL
  1038  	AVUSHLL2
  1039  	AVUXTL
  1040  	AVUXTL2
  1041  	AVUZP1
  1042  	AVUZP2
  1043  	AVSHL
  1044  	AVSRI
  1045  	AVSLI
  1046  	AVBSL
  1047  	AVBIT
  1048  	AVTBL
  1049  	AVXAR
  1050  	AVZIP1
  1051  	AVZIP2
  1052  	AVCMTST
  1053  	AVUADDW2
  1054  	AVUADDW
  1055  	AVUSRA
  1056  	ALAST
  1057  	AB  = obj.AJMP
  1058  	ABL = obj.ACALL
  1059  )
  1060  
  1061  const (
  1062  	// shift types
  1063  	SHIFT_LL = 0 << 22
  1064  	SHIFT_LR = 1 << 22
  1065  	SHIFT_AR = 2 << 22
  1066  )
  1067  
  1068  // Arrangement for ARM64 SIMD instructions
  1069  const (
  1070  	// arrangement types
  1071  	ARNG_8B = iota
  1072  	ARNG_16B
  1073  	ARNG_1D
  1074  	ARNG_4H
  1075  	ARNG_8H
  1076  	ARNG_2S
  1077  	ARNG_4S
  1078  	ARNG_2D
  1079  	ARNG_1Q
  1080  	ARNG_B
  1081  	ARNG_H
  1082  	ARNG_S
  1083  	ARNG_D
  1084  )
  1085  

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