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30 package ppc64
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "encoding/binary"
36 "fmt"
37 "log"
38 "math"
39 "sort"
40 )
41
42
43
44
45 type ctxt9 struct {
46 ctxt *obj.Link
47 newprog obj.ProgAlloc
48 cursym *obj.LSym
49 autosize int32
50 instoffset int64
51 pc int64
52 }
53
54
55
56 const (
57 funcAlign = 16
58 funcAlignMask = funcAlign - 1
59 )
60
61 const (
62 r0iszero = 1
63 )
64
65 type Optab struct {
66 as obj.As
67 a1 uint8
68 a2 uint8
69 a3 uint8
70 a4 uint8
71 a5 uint8
72 a6 uint8
73 type_ int8
74 size int8
75 }
76
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89
90
91 var optab = []Optab{
92 {as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0},
93 {as: obj.ATEXT, a1: C_LOREG, a3: C_LCON, a6: C_TEXTSIZE, type_: 0, size: 0},
94 {as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0},
95 {as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE, type_: 0, size: 0},
96
97 {as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
98 {as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4},
99 {as: AADD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
100 {as: AADD, a1: C_SCON, a6: C_REG, type_: 4, size: 4},
101 {as: AADD, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
102 {as: AADD, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4},
103 {as: AADD, a1: C_UCON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
104 {as: AADD, a1: C_UCON, a6: C_REG, type_: 20, size: 4},
105 {as: AADD, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 22, size: 8},
106 {as: AADD, a1: C_ANDCON, a6: C_REG, type_: 22, size: 8},
107 {as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
108 {as: AADD, a1: C_LCON, a6: C_REG, type_: 22, size: 12},
109 {as: AADDIS, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
110 {as: AADDIS, a1: C_ADDCON, a6: C_REG, type_: 20, size: 4},
111 {as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
112 {as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4},
113 {as: AADDC, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
114 {as: AADDC, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4},
115 {as: AADDC, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
116 {as: AADDC, a1: C_LCON, a6: C_REG, type_: 22, size: 12},
117 {as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
118 {as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4},
119 {as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
120 {as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4},
121 {as: AANDCC, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4},
122 {as: AANDCC, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
123 {as: AANDCC, a1: C_UCON, a6: C_REG, type_: 59, size: 4},
124 {as: AANDCC, a1: C_UCON, a2: C_REG, a6: C_REG, type_: 59, size: 4},
125 {as: AANDCC, a1: C_ADDCON, a6: C_REG, type_: 23, size: 8},
126 {as: AANDCC, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
127 {as: AANDCC, a1: C_LCON, a6: C_REG, type_: 23, size: 12},
128 {as: AANDCC, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
129 {as: AANDISCC, a1: C_ANDCON, a6: C_REG, type_: 59, size: 4},
130 {as: AANDISCC, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 59, size: 4},
131 {as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
132 {as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
133 {as: AMULLW, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
134 {as: AMULLW, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4},
135 {as: AMULLW, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
136 {as: AMULLW, a1: C_ANDCON, a6: C_REG, type_: 4, size: 4},
137 {as: AMULLW, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
138 {as: AMULLW, a1: C_LCON, a6: C_REG, type_: 22, size: 12},
139 {as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
140 {as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4},
141 {as: ASUBC, a1: C_REG, a3: C_ADDCON, a6: C_REG, type_: 27, size: 4},
142 {as: ASUBC, a1: C_REG, a3: C_LCON, a6: C_REG, type_: 28, size: 12},
143 {as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
144 {as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4},
145 {as: AOR, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4},
146 {as: AOR, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
147 {as: AOR, a1: C_UCON, a6: C_REG, type_: 59, size: 4},
148 {as: AOR, a1: C_UCON, a2: C_REG, a6: C_REG, type_: 59, size: 4},
149 {as: AOR, a1: C_ADDCON, a6: C_REG, type_: 23, size: 8},
150 {as: AOR, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
151 {as: AOR, a1: C_LCON, a6: C_REG, type_: 23, size: 12},
152 {as: AOR, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
153 {as: AORIS, a1: C_ANDCON, a6: C_REG, type_: 59, size: 4},
154 {as: AORIS, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 59, size: 4},
155 {as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
156 {as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
157 {as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
158 {as: ASUB, a1: C_REG, a6: C_REG, type_: 10, size: 4},
159 {as: ASLW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
160 {as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
161 {as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
162 {as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
163 {as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
164 {as: ASLD, a1: C_SCON, a6: C_REG, type_: 25, size: 4},
165 {as: AEXTSWSLI, a1: C_SCON, a6: C_REG, type_: 25, size: 4},
166 {as: AEXTSWSLI, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
167 {as: ASLW, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 57, size: 4},
168 {as: ASLW, a1: C_SCON, a6: C_REG, type_: 57, size: 4},
169 {as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
170 {as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
171 {as: ASRAW, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
172 {as: ASRAW, a1: C_SCON, a6: C_REG, type_: 56, size: 4},
173 {as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
174 {as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
175 {as: ASRAD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
176 {as: ASRAD, a1: C_SCON, a6: C_REG, type_: 56, size: 4},
177 {as: ARLWMI, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 62, size: 4},
178 {as: ARLWMI, a1: C_SCON, a2: C_REG, a3: C_SCON, a4: C_SCON, a6: C_REG, type_: 102, size: 4},
179 {as: ARLWMI, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 63, size: 4},
180 {as: ARLWMI, a1: C_REG, a2: C_REG, a3: C_SCON, a4: C_SCON, a6: C_REG, type_: 103, size: 4},
181 {as: ACLRLSLWI, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 62, size: 4},
182 {as: ARLDMI, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 30, size: 4},
183 {as: ARLDC, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 29, size: 4},
184 {as: ARLDCL, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 29, size: 4},
185 {as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
186 {as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
187 {as: ARLDICL, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
188 {as: ARLDCL, a1: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
189 {as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
190 {as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
191 {as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
192 {as: AFABS, a6: C_FREG, type_: 33, size: 4},
193 {as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
194 {as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
195 {as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4},
196
197 {as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
198 {as: AMOVBU, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
199
200 {as: AMOVBZU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
201 {as: AMOVBZU, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
202
203 {as: AMOVHBR, a1: C_REG, a6: C_ZOREG, type_: 44, size: 4},
204 {as: AMOVHBR, a1: C_ZOREG, a6: C_REG, type_: 45, size: 4},
205
206 {as: AMOVB, a1: C_ADDR, a6: C_REG, type_: 75, size: 12},
207 {as: AMOVB, a1: C_LOREG, a6: C_REG, type_: 36, size: 12},
208 {as: AMOVB, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
209 {as: AMOVB, a1: C_REG, a6: C_ADDR, type_: 74, size: 8},
210 {as: AMOVB, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
211 {as: AMOVB, a1: C_REG, a6: C_LOREG, type_: 35, size: 8},
212 {as: AMOVB, a1: C_REG, a6: C_REG, type_: 13, size: 4},
213
214 {as: AMOVBZ, a1: C_ADDR, a6: C_REG, type_: 75, size: 8},
215 {as: AMOVBZ, a1: C_LOREG, a6: C_REG, type_: 36, size: 8},
216 {as: AMOVBZ, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
217 {as: AMOVBZ, a1: C_REG, a6: C_ADDR, type_: 74, size: 8},
218 {as: AMOVBZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
219 {as: AMOVBZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8},
220 {as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
221
222 {as: AMOVD, a1: C_ADDCON, a6: C_REG, type_: 3, size: 4},
223 {as: AMOVD, a1: C_ANDCON, a6: C_REG, type_: 3, size: 4},
224 {as: AMOVD, a1: C_UCON, a6: C_REG, type_: 3, size: 4},
225 {as: AMOVD, a1: C_LCON, a6: C_REG, type_: 19, size: 8},
226 {as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
227 {as: AMOVD, a1: C_LACON, a6: C_REG, type_: 26, size: 8},
228 {as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8},
229 {as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
230 {as: AMOVD, a1: C_LOREG, a6: C_REG, type_: 36, size: 8},
231 {as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8},
232 {as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12},
233 {as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
234 {as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8},
235 {as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
236 {as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8},
237 {as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
238 {as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4},
239
240 {as: AMOVW, a1: C_ADDCON, a6: C_REG, type_: 3, size: 4},
241 {as: AMOVW, a1: C_ANDCON, a6: C_REG, type_: 3, size: 4},
242 {as: AMOVW, a1: C_UCON, a6: C_REG, type_: 3, size: 4},
243 {as: AMOVW, a1: C_LCON, a6: C_REG, type_: 19, size: 8},
244 {as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
245 {as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8},
246 {as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8},
247 {as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4},
248 {as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
249 {as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8},
250 {as: AMOVW, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
251 {as: AMOVW, a1: C_REG, a6: C_ADDR, type_: 74, size: 8},
252 {as: AMOVW, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
253 {as: AMOVW, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
254 {as: AMOVW, a1: C_REG, a6: C_LOREG, type_: 35, size: 8},
255 {as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
256 {as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4},
257
258 {as: AFMOVD, a1: C_ADDCON, a6: C_FREG, type_: 24, size: 8},
259 {as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4},
260 {as: AFMOVD, a1: C_LOREG, a6: C_FREG, type_: 36, size: 8},
261 {as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4},
262 {as: AFMOVD, a1: C_ADDR, a6: C_FREG, type_: 75, size: 8},
263 {as: AFMOVD, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
264 {as: AFMOVD, a1: C_FREG, a6: C_SOREG, type_: 7, size: 4},
265 {as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8},
266 {as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8},
267
268 {as: AFMOVSX, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
269 {as: AFMOVSX, a1: C_FREG, a6: C_ZOREG, type_: 44, size: 4},
270
271 {as: AFMOVSZ, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
272
273 {as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4},
274 {as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4},
275 {as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4},
276 {as: AMOVFL, a1: C_FREG, a3: C_LCON, a6: C_FPSCR, type_: 64, size: 4},
277 {as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4},
278 {as: AMOVFL, a1: C_LCON, a6: C_FPSCR, type_: 65, size: 4},
279 {as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
280 {as: AMOVFL, a1: C_REG, a6: C_LCON, type_: 69, size: 4},
281
282 {as: ASYSCALL, type_: 5, size: 4},
283 {as: ASYSCALL, a1: C_REG, type_: 77, size: 12},
284 {as: ASYSCALL, a1: C_SCON, type_: 77, size: 12},
285 {as: ABEQ, a6: C_SBRA, type_: 16, size: 4},
286 {as: ABEQ, a1: C_CREG, a6: C_SBRA, type_: 16, size: 4},
287 {as: ABR, a6: C_LBRA, type_: 11, size: 4},
288 {as: ABR, a6: C_LBRAPIC, type_: 11, size: 8},
289 {as: ABC, a1: C_SCON, a2: C_REG, a6: C_SBRA, type_: 16, size: 4},
290 {as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA, type_: 17, size: 4},
291 {as: ABR, a6: C_LR, type_: 18, size: 4},
292 {as: ABR, a3: C_SCON, a6: C_LR, type_: 18, size: 4},
293 {as: ABR, a6: C_CTR, type_: 18, size: 4},
294 {as: ABR, a1: C_REG, a6: C_CTR, type_: 18, size: 4},
295 {as: ABR, a6: C_ZOREG, type_: 15, size: 8},
296 {as: ABC, a2: C_REG, a6: C_LR, type_: 18, size: 4},
297 {as: ABC, a2: C_REG, a6: C_CTR, type_: 18, size: 4},
298 {as: ABC, a1: C_SCON, a2: C_REG, a6: C_LR, type_: 18, size: 4},
299 {as: ABC, a1: C_SCON, a2: C_REG, a6: C_CTR, type_: 18, size: 4},
300 {as: ABC, a6: C_ZOREG, type_: 15, size: 8},
301 {as: ASYNC, type_: 46, size: 4},
302 {as: AWORD, a1: C_LCON, type_: 40, size: 4},
303 {as: ADWORD, a1: C_LCON, type_: 31, size: 8},
304 {as: ADWORD, a1: C_DCON, type_: 31, size: 8},
305 {as: ADWORD, a1: C_LACON, type_: 31, size: 8},
306 {as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
307 {as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
308 {as: AEXTSB, a6: C_REG, type_: 48, size: 4},
309 {as: AISEL, a1: C_LCON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
310 {as: AISEL, a1: C_ZCON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
311 {as: ANEG, a1: C_REG, a6: C_REG, type_: 47, size: 4},
312 {as: ANEG, a6: C_REG, type_: 47, size: 4},
313 {as: AREM, a1: C_REG, a6: C_REG, type_: 50, size: 12},
314 {as: AREM, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 12},
315 {as: AREMU, a1: C_REG, a6: C_REG, type_: 50, size: 16},
316 {as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16},
317 {as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12},
318 {as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12},
319 {as: AMTFSB0, a1: C_SCON, type_: 52, size: 4},
320
321 {as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4},
322 {as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4},
323 {as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4},
324 {as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4},
325 {as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_SCON, type_: 92, size: 4},
326 {as: AFTSQRT, a1: C_FREG, a6: C_SCON, type_: 93, size: 4},
327 {as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4},
328 {as: ADARN, a1: C_SCON, a6: C_REG, type_: 92, size: 4},
329 {as: ALDMX, a1: C_SOREG, a6: C_REG, type_: 45, size: 4},
330 {as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4},
331 {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_SCON, a6: C_REG, type_: 94, size: 4},
332 {as: ACRAND, a1: C_CREG, a6: C_CREG, type_: 2, size: 4},
333
334
335
336
337 {as: ALV, a1: C_SOREG, a6: C_VREG, type_: 45, size: 4},
338
339
340 {as: ASTV, a1: C_VREG, a6: C_SOREG, type_: 44, size: 4},
341
342
343 {as: AVAND, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
344 {as: AVOR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
345
346
347 {as: AVADDUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
348 {as: AVADDCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
349 {as: AVADDUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
350 {as: AVADDSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
351 {as: AVADDE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
352
353
354 {as: AVSUBUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
355 {as: AVSUBCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
356 {as: AVSUBUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
357 {as: AVSUBSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
358 {as: AVSUBE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
359
360
361 {as: AVMULESB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
362 {as: AVPMSUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
363 {as: AVMSUMUDM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
364
365
366 {as: AVR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
367
368
369 {as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
370 {as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
371 {as: AVSOI, a1: C_ANDCON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
372
373
374 {as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
375 {as: AVPOPCNT, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
376
377
378 {as: AVCMPEQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
379 {as: AVCMPGT, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
380 {as: AVCMPNEZB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
381
382
383 {as: AVMRGOW, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
384
385
386 {as: AVPERM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
387
388
389 {as: AVBPERMQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
390
391
392 {as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
393
394
395 {as: AVSPLTB, a1: C_SCON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
396 {as: AVSPLTB, a1: C_ADDCON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
397 {as: AVSPLTISB, a1: C_SCON, a6: C_VREG, type_: 82, size: 4},
398 {as: AVSPLTISB, a1: C_ADDCON, a6: C_VREG, type_: 82, size: 4},
399
400
401 {as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
402 {as: AVNCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
403 {as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4},
404
405
406 {as: AVSHASIGMA, a1: C_ANDCON, a2: C_VREG, a3: C_ANDCON, a6: C_VREG, type_: 82, size: 4},
407
408
409 {as: ALXVD2X, a1: C_SOREG, a6: C_VSREG, type_: 87, size: 4},
410 {as: ALXV, a1: C_SOREG, a6: C_VSREG, type_: 96, size: 4},
411 {as: ALXVL, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 98, size: 4},
412
413
414 {as: ASTXVD2X, a1: C_VSREG, a6: C_SOREG, type_: 86, size: 4},
415 {as: ASTXV, a1: C_VSREG, a6: C_SOREG, type_: 97, size: 4},
416 {as: ASTXVL, a1: C_VSREG, a2: C_REG, a6: C_REG, type_: 99, size: 4},
417
418
419 {as: ALXSDX, a1: C_SOREG, a6: C_VSREG, type_: 87, size: 4},
420
421
422 {as: ASTXSDX, a1: C_VSREG, a6: C_SOREG, type_: 86, size: 4},
423
424
425 {as: ALXSIWAX, a1: C_SOREG, a6: C_VSREG, type_: 87, size: 4},
426
427
428 {as: ASTXSIWX, a1: C_VSREG, a6: C_SOREG, type_: 86, size: 4},
429
430
431 {as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4},
432 {as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4},
433 {as: AMFVSRD, a1: C_VREG, a6: C_REG, type_: 88, size: 4},
434
435
436 {as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 88, size: 4},
437 {as: AMTVSRD, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 88, size: 4},
438 {as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 88, size: 4},
439 {as: AMTVSRD, a1: C_REG, a6: C_VREG, type_: 88, size: 4},
440
441
442 {as: AXXLAND, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
443 {as: AXXLOR, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
444
445
446 {as: AXXSEL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, type_: 91, size: 4},
447
448
449 {as: AXXMRGHW, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
450
451
452 {as: AXXSPLTW, a1: C_VSREG, a3: C_SCON, a6: C_VSREG, type_: 89, size: 4},
453 {as: AXXSPLTIB, a1: C_SCON, a6: C_VSREG, type_: 100, size: 4},
454
455
456 {as: AXXPERM, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
457
458
459 {as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_SCON, a6: C_VSREG, type_: 90, size: 4},
460
461
462 {as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4},
463
464
465 {as: AXSCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
466
467
468 {as: AXVCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
469
470
471 {as: AXSCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
472
473
474 {as: AXSCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
475
476
477 {as: AXVCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
478
479
480 {as: AXVCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
481
482 {as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
483 {as: ACMP, a1: C_REG, a2: C_REG, a6: C_REG, type_: 70, size: 4},
484 {as: ACMP, a1: C_REG, a6: C_ADDCON, type_: 71, size: 4},
485 {as: ACMP, a1: C_REG, a2: C_REG, a6: C_ADDCON, type_: 71, size: 4},
486 {as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
487 {as: ACMPU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 70, size: 4},
488 {as: ACMPU, a1: C_REG, a6: C_ANDCON, type_: 71, size: 4},
489 {as: ACMPU, a1: C_REG, a2: C_REG, a6: C_ANDCON, type_: 71, size: 4},
490 {as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
491 {as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG, type_: 70, size: 4},
492 {as: ATW, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
493 {as: ATW, a1: C_LCON, a2: C_REG, a6: C_ADDCON, type_: 61, size: 4},
494 {as: ADCBF, a1: C_ZOREG, type_: 43, size: 4},
495 {as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
496 {as: ADCBF, a1: C_ZOREG, a2: C_REG, a6: C_SCON, type_: 43, size: 4},
497 {as: ADCBF, a1: C_SOREG, a6: C_SCON, type_: 43, size: 4},
498 {as: AECOWX, a1: C_REG, a2: C_REG, a6: C_ZOREG, type_: 44, size: 4},
499 {as: AECIWX, a1: C_ZOREG, a2: C_REG, a6: C_REG, type_: 45, size: 4},
500 {as: AECOWX, a1: C_REG, a6: C_ZOREG, type_: 44, size: 4},
501 {as: AECIWX, a1: C_ZOREG, a6: C_REG, type_: 45, size: 4},
502 {as: ALDAR, a1: C_ZOREG, a6: C_REG, type_: 45, size: 4},
503 {as: ALDAR, a1: C_ZOREG, a3: C_ANDCON, a6: C_REG, type_: 45, size: 4},
504 {as: AEIEIO, type_: 46, size: 4},
505 {as: ATLBIE, a1: C_REG, type_: 49, size: 4},
506 {as: ATLBIE, a1: C_SCON, a6: C_REG, type_: 49, size: 4},
507 {as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
508 {as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
509 {as: ASTSW, a1: C_REG, a6: C_ZOREG, type_: 44, size: 4},
510 {as: ASTSW, a1: C_REG, a3: C_LCON, a6: C_ZOREG, type_: 41, size: 4},
511 {as: ALSW, a1: C_ZOREG, a6: C_REG, type_: 45, size: 4},
512 {as: ALSW, a1: C_ZOREG, a3: C_LCON, a6: C_REG, type_: 42, size: 4},
513 {as: obj.AUNDEF, type_: 78, size: 4},
514 {as: obj.APCDATA, a1: C_LCON, a6: C_LCON, type_: 0, size: 0},
515 {as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR, type_: 0, size: 0},
516 {as: obj.ANOP, type_: 0, size: 0},
517 {as: obj.ANOP, a1: C_LCON, type_: 0, size: 0},
518 {as: obj.ANOP, a1: C_REG, type_: 0, size: 0},
519 {as: obj.ANOP, a1: C_FREG, type_: 0, size: 0},
520 {as: obj.ADUFFZERO, a6: C_LBRA, type_: 11, size: 4},
521 {as: obj.ADUFFCOPY, a6: C_LBRA, type_: 11, size: 4},
522 {as: obj.APCALIGN, a1: C_LCON, type_: 0, size: 0},
523
524 {as: obj.AXXX, type_: 0, size: 4},
525 }
526
527 var oprange [ALAST & obj.AMask][]Optab
528
529 var xcmp [C_NCLASS][C_NCLASS]bool
530
531
532 func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
533
534
535 switch a {
536 case 8:
537 if pc&7 != 0 {
538 return 4
539 }
540 case 16:
541
542
543 switch pc & 15 {
544 case 4, 12:
545 return 4
546 case 8:
547 return 8
548 }
549 case 32:
550
551
552 switch pc & 31 {
553 case 4, 20:
554 return 12
555 case 8, 24:
556 return 8
557 case 12, 28:
558 return 4
559 }
560
561
562
563
564
565 if ctxt.Headtype != objabi.Haix && cursym.Func().Align < 32 {
566 cursym.Func().Align = 32
567 }
568 default:
569 ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
570 }
571 return 0
572 }
573
574
575
576
577
578 func (c *ctxt9) getimpliedreg(a *obj.Addr, p *obj.Prog) int {
579 switch oclass(a) {
580 case C_ADDCON, C_ANDCON, C_UCON, C_LCON, C_SCON, C_ZCON:
581 return REGZERO
582 case C_SACON, C_LACON:
583 return REGSP
584 case C_LOREG, C_SOREG, C_ZOREG:
585 switch a.Name {
586 case obj.NAME_EXTERN, obj.NAME_STATIC:
587 return REGSB
588 case obj.NAME_AUTO, obj.NAME_PARAM:
589 return REGSP
590 case obj.NAME_NONE:
591 return REGZERO
592 }
593 }
594 c.ctxt.Diag("failed to determine implied reg for class %v (%v)", DRconv(oclass(a)), p)
595 return 0
596 }
597
598 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
599 p := cursym.Func().Text
600 if p == nil || p.Link == nil {
601 return
602 }
603
604 if oprange[AANDN&obj.AMask] == nil {
605 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
606 }
607
608 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
609
610 pc := int64(0)
611 p.Pc = pc
612
613 var m int
614 var o *Optab
615 for p = p.Link; p != nil; p = p.Link {
616 p.Pc = pc
617 o = c.oplook(p)
618 m = int(o.size)
619 if m == 0 {
620 if p.As == obj.APCALIGN {
621 a := c.vregoff(&p.From)
622 m = addpad(pc, a, ctxt, cursym)
623 } else {
624 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
625 ctxt.Diag("zero-width instruction\n%v", p)
626 }
627 continue
628 }
629 }
630 pc += int64(m)
631 }
632
633 c.cursym.Size = pc
634
635
641 bflag := 1
642
643 var otxt int64
644 var q *obj.Prog
645 for bflag != 0 {
646 bflag = 0
647 pc = 0
648 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
649 p.Pc = pc
650 o = c.oplook(p)
651
652
653 if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
654 otxt = p.To.Target().Pc - pc
655 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
656 q = c.newprog()
657 q.Link = p.Link
658 p.Link = q
659 q.As = ABR
660 q.To.Type = obj.TYPE_BRANCH
661 q.To.SetTarget(p.To.Target())
662 p.To.SetTarget(q)
663 q = c.newprog()
664 q.Link = p.Link
665 p.Link = q
666 q.As = ABR
667 q.To.Type = obj.TYPE_BRANCH
668 q.To.SetTarget(q.Link.Link)
669
670
671
672 bflag = 1
673 }
674 }
675
676 m = int(o.size)
677 if m == 0 {
678 if p.As == obj.APCALIGN {
679 a := c.vregoff(&p.From)
680 m = addpad(pc, a, ctxt, cursym)
681 } else {
682 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
683 ctxt.Diag("zero-width instruction\n%v", p)
684 }
685 continue
686 }
687 }
688
689 pc += int64(m)
690 }
691
692 c.cursym.Size = pc
693 }
694
695 if r := pc & funcAlignMask; r != 0 {
696 pc += funcAlign - r
697 }
698
699 c.cursym.Size = pc
700
701
704
705 c.cursym.Grow(c.cursym.Size)
706
707 bp := c.cursym.P
708 var i int32
709 var out [6]uint32
710 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
711 c.pc = p.Pc
712 o = c.oplook(p)
713 if int(o.size) > 4*len(out) {
714 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
715 }
716
717 if o.type_ == 0 && p.As == obj.APCALIGN {
718 pad := LOP_RRR(OP_OR, REGZERO, REGZERO, REGZERO)
719 aln := c.vregoff(&p.From)
720 v := addpad(p.Pc, aln, c.ctxt, c.cursym)
721 if v > 0 {
722
723 for i = 0; i < int32(v/4); i++ {
724 c.ctxt.Arch.ByteOrder.PutUint32(bp, pad)
725 bp = bp[4:]
726 }
727 }
728 } else {
729 c.asmout(p, o, out[:])
730 for i = 0; i < int32(o.size/4); i++ {
731 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
732 bp = bp[4:]
733 }
734 }
735 }
736 }
737
738 func isint32(v int64) bool {
739 return int64(int32(v)) == v
740 }
741
742 func isuint32(v uint64) bool {
743 return uint64(uint32(v)) == v
744 }
745
746 func (c *ctxt9) aclass(a *obj.Addr) int {
747 switch a.Type {
748 case obj.TYPE_NONE:
749 return C_NONE
750
751 case obj.TYPE_REG:
752 if REG_R0 <= a.Reg && a.Reg <= REG_R31 {
753 return C_REG
754 }
755 if REG_F0 <= a.Reg && a.Reg <= REG_F31 {
756 return C_FREG
757 }
758 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
759 return C_VREG
760 }
761 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 {
762 return C_VSREG
763 }
764 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR {
765 return C_CREG
766 }
767 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 {
768 switch a.Reg {
769 case REG_LR:
770 return C_LR
771
772 case REG_XER:
773 return C_XER
774
775 case REG_CTR:
776 return C_CTR
777 }
778
779 return C_SPR
780 }
781
782 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 {
783 return C_SPR
784 }
785 if a.Reg == REG_FPSCR {
786 return C_FPSCR
787 }
788 return C_GOK
789
790 case obj.TYPE_MEM:
791 switch a.Name {
792 case obj.NAME_GOTREF, obj.NAME_TOCREF:
793 return C_ADDR
794
795 case obj.NAME_EXTERN,
796 obj.NAME_STATIC:
797 c.instoffset = a.Offset
798 if a.Sym == nil {
799 break
800 } else if a.Sym.Type == objabi.STLSBSS {
801
802 if c.ctxt.Flag_shared {
803 return C_TLS_IE
804 }
805
806 return C_TLS_LE
807 } else {
808 return C_ADDR
809 }
810
811 case obj.NAME_AUTO:
812 c.instoffset = int64(c.autosize) + a.Offset
813 if c.instoffset >= -BIG && c.instoffset < BIG {
814 return C_SOREG
815 }
816 return C_LOREG
817
818 case obj.NAME_PARAM:
819 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
820 if c.instoffset >= -BIG && c.instoffset < BIG {
821 return C_SOREG
822 }
823 return C_LOREG
824
825 case obj.NAME_NONE:
826 c.instoffset = a.Offset
827 if c.instoffset == 0 {
828 return C_ZOREG
829 }
830 if c.instoffset >= -BIG && c.instoffset < BIG {
831 return C_SOREG
832 }
833 return C_LOREG
834 }
835
836 return C_GOK
837
838 case obj.TYPE_TEXTSIZE:
839 return C_TEXTSIZE
840
841 case obj.TYPE_FCONST:
842
843
844 f64 := a.Val.(float64)
845 if f64 == 0 {
846 if math.Signbit(f64) {
847 return C_ADDCON
848 }
849 return C_ZCON
850 }
851 log.Fatalf("Unexpected nonzero FCONST operand %v", a)
852
853 case obj.TYPE_CONST,
854 obj.TYPE_ADDR:
855 switch a.Name {
856 case obj.NAME_NONE:
857 c.instoffset = a.Offset
858 if a.Reg != 0 {
859 if -BIG <= c.instoffset && c.instoffset <= BIG {
860 return C_SACON
861 }
862 if isint32(c.instoffset) {
863 return C_LACON
864 }
865 return C_DACON
866 }
867
868 case obj.NAME_EXTERN,
869 obj.NAME_STATIC:
870 s := a.Sym
871 if s == nil {
872 return C_GOK
873 }
874 c.instoffset = a.Offset
875 return C_LACON
876
877 case obj.NAME_AUTO:
878 c.instoffset = int64(c.autosize) + a.Offset
879 if c.instoffset >= -BIG && c.instoffset < BIG {
880 return C_SACON
881 }
882 return C_LACON
883
884 case obj.NAME_PARAM:
885 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
886 if c.instoffset >= -BIG && c.instoffset < BIG {
887 return C_SACON
888 }
889 return C_LACON
890
891 default:
892 return C_GOK
893 }
894
895 if c.instoffset >= 0 {
896 if c.instoffset == 0 {
897 return C_ZCON
898 }
899 if c.instoffset <= 0x7fff {
900 return C_SCON
901 }
902 if c.instoffset <= 0xffff {
903 return C_ANDCON
904 }
905 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
906 return C_UCON
907 }
908 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
909 return C_LCON
910 }
911 return C_DCON
912 }
913
914 if c.instoffset >= -0x8000 {
915 return C_ADDCON
916 }
917 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
918 return C_UCON
919 }
920 if isint32(c.instoffset) {
921 return C_LCON
922 }
923 return C_DCON
924
925 case obj.TYPE_BRANCH:
926 if a.Sym != nil && c.ctxt.Flag_dynlink {
927 return C_LBRAPIC
928 }
929 return C_SBRA
930 }
931
932 return C_GOK
933 }
934
935 func prasm(p *obj.Prog) {
936 fmt.Printf("%v\n", p)
937 }
938
939 func (c *ctxt9) oplook(p *obj.Prog) *Optab {
940 a1 := int(p.Optab)
941 if a1 != 0 {
942 return &optab[a1-1]
943 }
944 a1 = int(p.From.Class)
945 if a1 == 0 {
946 a1 = c.aclass(&p.From) + 1
947 p.From.Class = int8(a1)
948 }
949 a1--
950
951 argsv := [3]int{C_NONE + 1, C_NONE + 1, C_NONE + 1}
952 for i, ap := range p.RestArgs {
953 argsv[i] = int(ap.Addr.Class)
954 if argsv[i] == 0 {
955 argsv[i] = c.aclass(&ap.Addr) + 1
956 ap.Addr.Class = int8(argsv[i])
957 }
958
959 }
960 a3 := argsv[0] - 1
961 a4 := argsv[1] - 1
962 a5 := argsv[2] - 1
963
964 a6 := int(p.To.Class)
965 if a6 == 0 {
966 a6 = c.aclass(&p.To) + 1
967 p.To.Class = int8(a6)
968 }
969 a6--
970
971 a2 := C_NONE
972 if p.Reg != 0 {
973 if REG_R0 <= p.Reg && p.Reg <= REG_R31 {
974 a2 = C_REG
975 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 {
976 a2 = C_VREG
977 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 {
978 a2 = C_VSREG
979 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 {
980 a2 = C_FREG
981 }
982 }
983
984
985 ops := oprange[p.As&obj.AMask]
986 c1 := &xcmp[a1]
987 c3 := &xcmp[a3]
988 c4 := &xcmp[a4]
989 c5 := &xcmp[a5]
990 c6 := &xcmp[a6]
991 for i := range ops {
992 op := &ops[i]
993 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] && c5[op.a5] && c6[op.a6] {
994 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
995 return op
996 }
997 }
998
999 c.ctxt.Diag("illegal combination %v %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5), DRconv(a6))
1000 prasm(p)
1001 if ops == nil {
1002 ops = optab
1003 }
1004 return &ops[0]
1005 }
1006
1007 func cmp(a int, b int) bool {
1008 if a == b {
1009 return true
1010 }
1011 switch a {
1012 case C_LCON:
1013 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
1014 return true
1015 }
1016
1017 case C_ADDCON:
1018 if b == C_ZCON || b == C_SCON {
1019 return true
1020 }
1021
1022 case C_ANDCON:
1023 if b == C_ZCON || b == C_SCON {
1024 return true
1025 }
1026
1027 case C_SPR:
1028 if b == C_LR || b == C_XER || b == C_CTR {
1029 return true
1030 }
1031
1032 case C_UCON:
1033 if b == C_ZCON {
1034 return true
1035 }
1036
1037 case C_SCON:
1038 if b == C_ZCON {
1039 return true
1040 }
1041
1042 case C_LACON:
1043 if b == C_SACON {
1044 return true
1045 }
1046
1047 case C_LBRA:
1048 if b == C_SBRA {
1049 return true
1050 }
1051
1052 case C_SOREG:
1053 if b == C_ZOREG {
1054 return true
1055 }
1056
1057 case C_LOREG:
1058 if b == C_SOREG || b == C_ZOREG {
1059 return true
1060 }
1061
1062 case C_REG:
1063 if b == C_ZCON {
1064 return r0iszero != 0
1065 }
1066
1067 case C_ANY:
1068 return true
1069 }
1070
1071 return false
1072 }
1073
1074 type ocmp []Optab
1075
1076 func (x ocmp) Len() int {
1077 return len(x)
1078 }
1079
1080 func (x ocmp) Swap(i, j int) {
1081 x[i], x[j] = x[j], x[i]
1082 }
1083
1084
1085
1086
1087 func (x ocmp) Less(i, j int) bool {
1088 p1 := &x[i]
1089 p2 := &x[j]
1090 n := int(p1.as) - int(p2.as)
1091
1092 if n != 0 {
1093 return n < 0
1094 }
1095
1096
1097 n = int(p1.size) - int(p2.size)
1098 if n != 0 {
1099 return n < 0
1100 }
1101
1102
1103 n = int(p1.a1) - int(p2.a1)
1104 if n != 0 {
1105 return n < 0
1106 }
1107 n = int(p1.a2) - int(p2.a2)
1108 if n != 0 {
1109 return n < 0
1110 }
1111 n = int(p1.a3) - int(p2.a3)
1112 if n != 0 {
1113 return n < 0
1114 }
1115 n = int(p1.a4) - int(p2.a4)
1116 if n != 0 {
1117 return n < 0
1118 }
1119 n = int(p1.a5) - int(p2.a5)
1120 if n != 0 {
1121 return n < 0
1122 }
1123 n = int(p1.a6) - int(p2.a6)
1124 if n != 0 {
1125 return n < 0
1126 }
1127 return false
1128 }
1129
1130
1131
1132
1133 func opset(a, b0 obj.As) {
1134 oprange[a&obj.AMask] = oprange[b0]
1135 }
1136
1137
1138 func buildop(ctxt *obj.Link) {
1139 if oprange[AANDN&obj.AMask] != nil {
1140
1141
1142
1143 return
1144 }
1145
1146 var n int
1147
1148 for i := 0; i < C_NCLASS; i++ {
1149 for n = 0; n < C_NCLASS; n++ {
1150 if cmp(n, i) {
1151 xcmp[i][n] = true
1152 }
1153 }
1154 }
1155 for n = 0; optab[n].as != obj.AXXX; n++ {
1156 }
1157 sort.Sort(ocmp(optab[:n]))
1158 for i := 0; i < n; i++ {
1159 r := optab[i].as
1160 r0 := r & obj.AMask
1161 start := i
1162 for optab[i].as == r {
1163 i++
1164 }
1165 oprange[r0] = optab[start:i]
1166 i--
1167
1168 switch r {
1169 default:
1170 ctxt.Diag("unknown op in build: %v", r)
1171 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
1172
1173 case ADCBF:
1174 opset(ADCBI, r0)
1175
1176 opset(ADCBST, r0)
1177 opset(ADCBT, r0)
1178 opset(ADCBTST, r0)
1179 opset(ADCBZ, r0)
1180 opset(AICBI, r0)
1181
1182 case AECOWX:
1183 opset(ASTWCCC, r0)
1184 opset(ASTHCCC, r0)
1185 opset(ASTBCCC, r0)
1186 opset(ASTDCCC, r0)
1187
1188 case AREM:
1189 opset(AREM, r0)
1190
1191 case AREMU:
1192 opset(AREMU, r0)
1193
1194 case AREMD:
1195 opset(AREMDU, r0)
1196
1197 case AMULLW:
1198 opset(AMULLD, r0)
1199
1200 case ADIVW:
1201 opset(AMULHW, r0)
1202
1203 opset(AMULHWCC, r0)
1204 opset(AMULHWU, r0)
1205 opset(AMULHWUCC, r0)
1206 opset(AMULLWCC, r0)
1207 opset(AMULLWVCC, r0)
1208 opset(AMULLWV, r0)
1209 opset(ADIVWCC, r0)
1210 opset(ADIVWV, r0)
1211 opset(ADIVWVCC, r0)
1212 opset(ADIVWU, r0)
1213 opset(ADIVWUCC, r0)
1214 opset(ADIVWUV, r0)
1215 opset(ADIVWUVCC, r0)
1216 opset(AMODUD, r0)
1217 opset(AMODUW, r0)
1218 opset(AMODSD, r0)
1219 opset(AMODSW, r0)
1220 opset(AADDCC, r0)
1221 opset(AADDCV, r0)
1222 opset(AADDCVCC, r0)
1223 opset(AADDV, r0)
1224 opset(AADDVCC, r0)
1225 opset(AADDE, r0)
1226 opset(AADDECC, r0)
1227 opset(AADDEV, r0)
1228 opset(AADDEVCC, r0)
1229 opset(AMULHD, r0)
1230 opset(AMULHDCC, r0)
1231 opset(AMULHDU, r0)
1232 opset(AMULHDUCC, r0)
1233 opset(AMULLDCC, r0)
1234 opset(AMULLDVCC, r0)
1235 opset(AMULLDV, r0)
1236 opset(ADIVD, r0)
1237 opset(ADIVDCC, r0)
1238 opset(ADIVDE, r0)
1239 opset(ADIVDEU, r0)
1240 opset(ADIVDECC, r0)
1241 opset(ADIVDEUCC, r0)
1242 opset(ADIVDVCC, r0)
1243 opset(ADIVDV, r0)
1244 opset(ADIVDU, r0)
1245 opset(ADIVDUV, r0)
1246 opset(ADIVDUVCC, r0)
1247 opset(ADIVDUCC, r0)
1248
1249 case ACRAND:
1250 opset(ACRANDN, r0)
1251 opset(ACREQV, r0)
1252 opset(ACRNAND, r0)
1253 opset(ACRNOR, r0)
1254 opset(ACROR, r0)
1255 opset(ACRORN, r0)
1256 opset(ACRXOR, r0)
1257
1258 case APOPCNTD:
1259 opset(APOPCNTW, r0)
1260 opset(APOPCNTB, r0)
1261 opset(ACNTTZW, r0)
1262 opset(ACNTTZWCC, r0)
1263 opset(ACNTTZD, r0)
1264 opset(ACNTTZDCC, r0)
1265
1266 case ACOPY:
1267 opset(APASTECC, r0)
1268
1269 case AMADDHD:
1270 opset(AMADDHDU, r0)
1271 opset(AMADDLD, r0)
1272
1273 case AMOVBZ:
1274 opset(AMOVH, r0)
1275 opset(AMOVHZ, r0)
1276
1277 case AMOVBZU:
1278 opset(AMOVHU, r0)
1279
1280 opset(AMOVHZU, r0)
1281 opset(AMOVWU, r0)
1282 opset(AMOVWZU, r0)
1283 opset(AMOVDU, r0)
1284 opset(AMOVMW, r0)
1285
1286 case ALV:
1287 opset(ALVEBX, r0)
1288 opset(ALVEHX, r0)
1289 opset(ALVEWX, r0)
1290 opset(ALVX, r0)
1291 opset(ALVXL, r0)
1292 opset(ALVSL, r0)
1293 opset(ALVSR, r0)
1294
1295 case ASTV:
1296 opset(ASTVEBX, r0)
1297 opset(ASTVEHX, r0)
1298 opset(ASTVEWX, r0)
1299 opset(ASTVX, r0)
1300 opset(ASTVXL, r0)
1301
1302 case AVAND:
1303 opset(AVAND, r0)
1304 opset(AVANDC, r0)
1305 opset(AVNAND, r0)
1306
1307 case AVMRGOW:
1308 opset(AVMRGEW, r0)
1309
1310 case AVOR:
1311 opset(AVOR, r0)
1312 opset(AVORC, r0)
1313 opset(AVXOR, r0)
1314 opset(AVNOR, r0)
1315 opset(AVEQV, r0)
1316
1317 case AVADDUM:
1318 opset(AVADDUBM, r0)
1319 opset(AVADDUHM, r0)
1320 opset(AVADDUWM, r0)
1321 opset(AVADDUDM, r0)
1322 opset(AVADDUQM, r0)
1323
1324 case AVADDCU:
1325 opset(AVADDCUQ, r0)
1326 opset(AVADDCUW, r0)
1327
1328 case AVADDUS:
1329 opset(AVADDUBS, r0)
1330 opset(AVADDUHS, r0)
1331 opset(AVADDUWS, r0)
1332
1333 case AVADDSS:
1334 opset(AVADDSBS, r0)
1335 opset(AVADDSHS, r0)
1336 opset(AVADDSWS, r0)
1337
1338 case AVADDE:
1339 opset(AVADDEUQM, r0)
1340 opset(AVADDECUQ, r0)
1341
1342 case AVSUBUM:
1343 opset(AVSUBUBM, r0)
1344 opset(AVSUBUHM, r0)
1345 opset(AVSUBUWM, r0)
1346 opset(AVSUBUDM, r0)
1347 opset(AVSUBUQM, r0)
1348
1349 case AVSUBCU:
1350 opset(AVSUBCUQ, r0)
1351 opset(AVSUBCUW, r0)
1352
1353 case AVSUBUS:
1354 opset(AVSUBUBS, r0)
1355 opset(AVSUBUHS, r0)
1356 opset(AVSUBUWS, r0)
1357
1358 case AVSUBSS:
1359 opset(AVSUBSBS, r0)
1360 opset(AVSUBSHS, r0)
1361 opset(AVSUBSWS, r0)
1362
1363 case AVSUBE:
1364 opset(AVSUBEUQM, r0)
1365 opset(AVSUBECUQ, r0)
1366
1367 case AVMULESB:
1368 opset(AVMULOSB, r0)
1369 opset(AVMULEUB, r0)
1370 opset(AVMULOUB, r0)
1371 opset(AVMULESH, r0)
1372 opset(AVMULOSH, r0)
1373 opset(AVMULEUH, r0)
1374 opset(AVMULOUH, r0)
1375 opset(AVMULESW, r0)
1376 opset(AVMULOSW, r0)
1377 opset(AVMULEUW, r0)
1378 opset(AVMULOUW, r0)
1379 opset(AVMULUWM, r0)
1380 case AVPMSUM:
1381 opset(AVPMSUMB, r0)
1382 opset(AVPMSUMH, r0)
1383 opset(AVPMSUMW, r0)
1384 opset(AVPMSUMD, r0)
1385
1386 case AVR:
1387 opset(AVRLB, r0)
1388 opset(AVRLH, r0)
1389 opset(AVRLW, r0)
1390 opset(AVRLD, r0)
1391
1392 case AVS:
1393 opset(AVSLB, r0)
1394 opset(AVSLH, r0)
1395 opset(AVSLW, r0)
1396 opset(AVSL, r0)
1397 opset(AVSLO, r0)
1398 opset(AVSRB, r0)
1399 opset(AVSRH, r0)
1400 opset(AVSRW, r0)
1401 opset(AVSR, r0)
1402 opset(AVSRO, r0)
1403 opset(AVSLD, r0)
1404 opset(AVSRD, r0)
1405
1406 case AVSA:
1407 opset(AVSRAB, r0)
1408 opset(AVSRAH, r0)
1409 opset(AVSRAW, r0)
1410 opset(AVSRAD, r0)
1411
1412 case AVSOI:
1413 opset(AVSLDOI, r0)
1414
1415 case AVCLZ:
1416 opset(AVCLZB, r0)
1417 opset(AVCLZH, r0)
1418 opset(AVCLZW, r0)
1419 opset(AVCLZD, r0)
1420
1421 case AVPOPCNT:
1422 opset(AVPOPCNTB, r0)
1423 opset(AVPOPCNTH, r0)
1424 opset(AVPOPCNTW, r0)
1425 opset(AVPOPCNTD, r0)
1426
1427 case AVCMPEQ:
1428 opset(AVCMPEQUB, r0)
1429 opset(AVCMPEQUBCC, r0)
1430 opset(AVCMPEQUH, r0)
1431 opset(AVCMPEQUHCC, r0)
1432 opset(AVCMPEQUW, r0)
1433 opset(AVCMPEQUWCC, r0)
1434 opset(AVCMPEQUD, r0)
1435 opset(AVCMPEQUDCC, r0)
1436
1437 case AVCMPGT:
1438 opset(AVCMPGTUB, r0)
1439 opset(AVCMPGTUBCC, r0)
1440 opset(AVCMPGTUH, r0)
1441 opset(AVCMPGTUHCC, r0)
1442 opset(AVCMPGTUW, r0)
1443 opset(AVCMPGTUWCC, r0)
1444 opset(AVCMPGTUD, r0)
1445 opset(AVCMPGTUDCC, r0)
1446 opset(AVCMPGTSB, r0)
1447 opset(AVCMPGTSBCC, r0)
1448 opset(AVCMPGTSH, r0)
1449 opset(AVCMPGTSHCC, r0)
1450 opset(AVCMPGTSW, r0)
1451 opset(AVCMPGTSWCC, r0)
1452 opset(AVCMPGTSD, r0)
1453 opset(AVCMPGTSDCC, r0)
1454
1455 case AVCMPNEZB:
1456 opset(AVCMPNEZBCC, r0)
1457 opset(AVCMPNEB, r0)
1458 opset(AVCMPNEBCC, r0)
1459 opset(AVCMPNEH, r0)
1460 opset(AVCMPNEHCC, r0)
1461 opset(AVCMPNEW, r0)
1462 opset(AVCMPNEWCC, r0)
1463
1464 case AVPERM:
1465 opset(AVPERMXOR, r0)
1466 opset(AVPERMR, r0)
1467
1468 case AVBPERMQ:
1469 opset(AVBPERMD, r0)
1470
1471 case AVSEL:
1472 opset(AVSEL, r0)
1473
1474 case AVSPLTB:
1475 opset(AVSPLTH, r0)
1476 opset(AVSPLTW, r0)
1477
1478 case AVSPLTISB:
1479 opset(AVSPLTISH, r0)
1480 opset(AVSPLTISW, r0)
1481
1482 case AVCIPH:
1483 opset(AVCIPHER, r0)
1484 opset(AVCIPHERLAST, r0)
1485
1486 case AVNCIPH:
1487 opset(AVNCIPHER, r0)
1488 opset(AVNCIPHERLAST, r0)
1489
1490 case AVSBOX:
1491 opset(AVSBOX, r0)
1492
1493 case AVSHASIGMA:
1494 opset(AVSHASIGMAW, r0)
1495 opset(AVSHASIGMAD, r0)
1496
1497 case ALXVD2X:
1498 opset(ALXVDSX, r0)
1499 opset(ALXVW4X, r0)
1500 opset(ALXVH8X, r0)
1501 opset(ALXVB16X, r0)
1502
1503 case ALXV:
1504 opset(ALXV, r0)
1505
1506 case ALXVL:
1507 opset(ALXVLL, r0)
1508 opset(ALXVX, r0)
1509
1510 case ASTXVD2X:
1511 opset(ASTXVW4X, r0)
1512 opset(ASTXVH8X, r0)
1513 opset(ASTXVB16X, r0)
1514
1515 case ASTXV:
1516 opset(ASTXV, r0)
1517
1518 case ASTXVL:
1519 opset(ASTXVLL, r0)
1520 opset(ASTXVX, r0)
1521
1522 case ALXSDX:
1523 opset(ALXSDX, r0)
1524
1525 case ASTXSDX:
1526 opset(ASTXSDX, r0)
1527
1528 case ALXSIWAX:
1529 opset(ALXSIWZX, r0)
1530
1531 case ASTXSIWX:
1532 opset(ASTXSIWX, r0)
1533
1534 case AMFVSRD:
1535 opset(AMFFPRD, r0)
1536 opset(AMFVRD, r0)
1537 opset(AMFVSRWZ, r0)
1538 opset(AMFVSRLD, r0)
1539
1540 case AMTVSRD:
1541 opset(AMTFPRD, r0)
1542 opset(AMTVRD, r0)
1543 opset(AMTVSRWA, r0)
1544 opset(AMTVSRWZ, r0)
1545 opset(AMTVSRDD, r0)
1546 opset(AMTVSRWS, r0)
1547
1548 case AXXLAND:
1549 opset(AXXLANDC, r0)
1550 opset(AXXLEQV, r0)
1551 opset(AXXLNAND, r0)
1552
1553 case AXXLOR:
1554 opset(AXXLORC, r0)
1555 opset(AXXLNOR, r0)
1556 opset(AXXLORQ, r0)
1557 opset(AXXLXOR, r0)
1558
1559 case AXXSEL:
1560 opset(AXXSEL, r0)
1561
1562 case AXXMRGHW:
1563 opset(AXXMRGLW, r0)
1564
1565 case AXXSPLTW:
1566 opset(AXXSPLTW, r0)
1567
1568 case AXXSPLTIB:
1569 opset(AXXSPLTIB, r0)
1570
1571 case AXXPERM:
1572 opset(AXXPERM, r0)
1573
1574 case AXXSLDWI:
1575 opset(AXXPERMDI, r0)
1576 opset(AXXSLDWI, r0)
1577
1578 case AXXBRQ:
1579 opset(AXXBRD, r0)
1580 opset(AXXBRW, r0)
1581 opset(AXXBRH, r0)
1582
1583 case AXSCVDPSP:
1584 opset(AXSCVSPDP, r0)
1585 opset(AXSCVDPSPN, r0)
1586 opset(AXSCVSPDPN, r0)
1587
1588 case AXVCVDPSP:
1589 opset(AXVCVSPDP, r0)
1590
1591 case AXSCVDPSXDS:
1592 opset(AXSCVDPSXWS, r0)
1593 opset(AXSCVDPUXDS, r0)
1594 opset(AXSCVDPUXWS, r0)
1595
1596 case AXSCVSXDDP:
1597 opset(AXSCVUXDDP, r0)
1598 opset(AXSCVSXDSP, r0)
1599 opset(AXSCVUXDSP, r0)
1600
1601 case AXVCVDPSXDS:
1602 opset(AXVCVDPSXDS, r0)
1603 opset(AXVCVDPSXWS, r0)
1604 opset(AXVCVDPUXDS, r0)
1605 opset(AXVCVDPUXWS, r0)
1606 opset(AXVCVSPSXDS, r0)
1607 opset(AXVCVSPSXWS, r0)
1608 opset(AXVCVSPUXDS, r0)
1609 opset(AXVCVSPUXWS, r0)
1610
1611 case AXVCVSXDDP:
1612 opset(AXVCVSXWDP, r0)
1613 opset(AXVCVUXDDP, r0)
1614 opset(AXVCVUXWDP, r0)
1615 opset(AXVCVSXDSP, r0)
1616 opset(AXVCVSXWSP, r0)
1617 opset(AXVCVUXDSP, r0)
1618 opset(AXVCVUXWSP, r0)
1619
1620 case AAND:
1621 opset(AANDN, r0)
1622 opset(AANDNCC, r0)
1623 opset(AEQV, r0)
1624 opset(AEQVCC, r0)
1625 opset(ANAND, r0)
1626 opset(ANANDCC, r0)
1627 opset(ANOR, r0)
1628 opset(ANORCC, r0)
1629 opset(AORCC, r0)
1630 opset(AORN, r0)
1631 opset(AORNCC, r0)
1632 opset(AXORCC, r0)
1633
1634 case AADDME:
1635 opset(AADDMECC, r0)
1636
1637 opset(AADDMEV, r0)
1638 opset(AADDMEVCC, r0)
1639 opset(AADDZE, r0)
1640 opset(AADDZECC, r0)
1641 opset(AADDZEV, r0)
1642 opset(AADDZEVCC, r0)
1643 opset(ASUBME, r0)
1644 opset(ASUBMECC, r0)
1645 opset(ASUBMEV, r0)
1646 opset(ASUBMEVCC, r0)
1647 opset(ASUBZE, r0)
1648 opset(ASUBZECC, r0)
1649 opset(ASUBZEV, r0)
1650 opset(ASUBZEVCC, r0)
1651
1652 case AADDC:
1653 opset(AADDCCC, r0)
1654
1655 case ABEQ:
1656 opset(ABGE, r0)
1657 opset(ABGT, r0)
1658 opset(ABLE, r0)
1659 opset(ABLT, r0)
1660 opset(ABNE, r0)
1661 opset(ABVC, r0)
1662 opset(ABVS, r0)
1663
1664 case ABR:
1665 opset(ABL, r0)
1666
1667 case ABC:
1668 opset(ABCL, r0)
1669
1670 case AEXTSB:
1671 opset(AEXTSBCC, r0)
1672
1673 opset(AEXTSH, r0)
1674 opset(AEXTSHCC, r0)
1675 opset(ACNTLZW, r0)
1676 opset(ACNTLZWCC, r0)
1677 opset(ACNTLZD, r0)
1678 opset(AEXTSW, r0)
1679 opset(AEXTSWCC, r0)
1680 opset(ACNTLZDCC, r0)
1681
1682 case AFABS:
1683 opset(AFABSCC, r0)
1684
1685 opset(AFNABS, r0)
1686 opset(AFNABSCC, r0)
1687 opset(AFNEG, r0)
1688 opset(AFNEGCC, r0)
1689 opset(AFRSP, r0)
1690 opset(AFRSPCC, r0)
1691 opset(AFCTIW, r0)
1692 opset(AFCTIWCC, r0)
1693 opset(AFCTIWZ, r0)
1694 opset(AFCTIWZCC, r0)
1695 opset(AFCTID, r0)
1696 opset(AFCTIDCC, r0)
1697 opset(AFCTIDZ, r0)
1698 opset(AFCTIDZCC, r0)
1699 opset(AFCFID, r0)
1700 opset(AFCFIDCC, r0)
1701 opset(AFCFIDU, r0)
1702 opset(AFCFIDUCC, r0)
1703 opset(AFCFIDS, r0)
1704 opset(AFCFIDSCC, r0)
1705 opset(AFRES, r0)
1706 opset(AFRESCC, r0)
1707 opset(AFRIM, r0)
1708 opset(AFRIMCC, r0)
1709 opset(AFRIP, r0)
1710 opset(AFRIPCC, r0)
1711 opset(AFRIZ, r0)
1712 opset(AFRIZCC, r0)
1713 opset(AFRIN, r0)
1714 opset(AFRINCC, r0)
1715 opset(AFRSQRTE, r0)
1716 opset(AFRSQRTECC, r0)
1717 opset(AFSQRT, r0)
1718 opset(AFSQRTCC, r0)
1719 opset(AFSQRTS, r0)
1720 opset(AFSQRTSCC, r0)
1721
1722 case AFADD:
1723 opset(AFADDS, r0)
1724 opset(AFADDCC, r0)
1725 opset(AFADDSCC, r0)
1726 opset(AFCPSGN, r0)
1727 opset(AFCPSGNCC, r0)
1728 opset(AFDIV, r0)
1729 opset(AFDIVS, r0)
1730 opset(AFDIVCC, r0)
1731 opset(AFDIVSCC, r0)
1732 opset(AFSUB, r0)
1733 opset(AFSUBS, r0)
1734 opset(AFSUBCC, r0)
1735 opset(AFSUBSCC, r0)
1736
1737 case AFMADD:
1738 opset(AFMADDCC, r0)
1739 opset(AFMADDS, r0)
1740 opset(AFMADDSCC, r0)
1741 opset(AFMSUB, r0)
1742 opset(AFMSUBCC, r0)
1743 opset(AFMSUBS, r0)
1744 opset(AFMSUBSCC, r0)
1745 opset(AFNMADD, r0)
1746 opset(AFNMADDCC, r0)
1747 opset(AFNMADDS, r0)
1748 opset(AFNMADDSCC, r0)
1749 opset(AFNMSUB, r0)
1750 opset(AFNMSUBCC, r0)
1751 opset(AFNMSUBS, r0)
1752 opset(AFNMSUBSCC, r0)
1753 opset(AFSEL, r0)
1754 opset(AFSELCC, r0)
1755
1756 case AFMUL:
1757 opset(AFMULS, r0)
1758 opset(AFMULCC, r0)
1759 opset(AFMULSCC, r0)
1760
1761 case AFCMPO:
1762 opset(AFCMPU, r0)
1763
1764 case AISEL:
1765 opset(AISEL, r0)
1766
1767 case AMTFSB0:
1768 opset(AMTFSB0CC, r0)
1769 opset(AMTFSB1, r0)
1770 opset(AMTFSB1CC, r0)
1771
1772 case ANEG:
1773 opset(ANEGCC, r0)
1774
1775 opset(ANEGV, r0)
1776 opset(ANEGVCC, r0)
1777
1778 case AOR:
1779 opset(AXOR, r0)
1780
1781 case AORIS:
1782 opset(AXORIS, r0)
1783
1784 case ASLW:
1785 opset(ASLWCC, r0)
1786 opset(ASRW, r0)
1787 opset(ASRWCC, r0)
1788 opset(AROTLW, r0)
1789
1790 case ASLD:
1791 opset(ASLDCC, r0)
1792 opset(ASRD, r0)
1793 opset(ASRDCC, r0)
1794 opset(AROTL, r0)
1795
1796 case ASRAW:
1797 opset(ASRAWCC, r0)
1798
1799 case AEXTSWSLI:
1800 opset(AEXTSWSLICC, r0)
1801
1802 case ASRAD:
1803 opset(ASRADCC, r0)
1804
1805 case ASUB:
1806 opset(ASUB, r0)
1807
1808 opset(ASUBCC, r0)
1809 opset(ASUBV, r0)
1810 opset(ASUBVCC, r0)
1811 opset(ASUBCCC, r0)
1812 opset(ASUBCV, r0)
1813 opset(ASUBCVCC, r0)
1814 opset(ASUBE, r0)
1815 opset(ASUBECC, r0)
1816 opset(ASUBEV, r0)
1817 opset(ASUBEVCC, r0)
1818
1819 case ASYNC:
1820 opset(AISYNC, r0)
1821 opset(ALWSYNC, r0)
1822 opset(APTESYNC, r0)
1823 opset(ATLBSYNC, r0)
1824
1825 case ARLWMI:
1826 opset(ARLWMICC, r0)
1827 opset(ARLWNM, r0)
1828 opset(ARLWNMCC, r0)
1829
1830 case ARLDMI:
1831 opset(ARLDMICC, r0)
1832 opset(ARLDIMI, r0)
1833 opset(ARLDIMICC, r0)
1834
1835 case ARLDC:
1836 opset(ARLDCCC, r0)
1837
1838 case ARLDCL:
1839 opset(ARLDCR, r0)
1840 opset(ARLDCLCC, r0)
1841 opset(ARLDCRCC, r0)
1842
1843 case ARLDICL:
1844 opset(ARLDICLCC, r0)
1845 opset(ARLDICR, r0)
1846 opset(ARLDICRCC, r0)
1847 opset(ARLDIC, r0)
1848 opset(ARLDICCC, r0)
1849 opset(ACLRLSLDI, r0)
1850
1851 case AFMOVD:
1852 opset(AFMOVDCC, r0)
1853 opset(AFMOVDU, r0)
1854 opset(AFMOVS, r0)
1855 opset(AFMOVSU, r0)
1856
1857 case ALDAR:
1858 opset(ALBAR, r0)
1859 opset(ALHAR, r0)
1860 opset(ALWAR, r0)
1861
1862 case ASYSCALL:
1863 opset(ARFI, r0)
1864
1865 opset(ARFCI, r0)
1866 opset(ARFID, r0)
1867 opset(AHRFID, r0)
1868
1869 case AMOVHBR:
1870 opset(AMOVWBR, r0)
1871 opset(AMOVDBR, r0)
1872
1873 case ASLBMFEE:
1874 opset(ASLBMFEV, r0)
1875
1876 case ATW:
1877 opset(ATD, r0)
1878
1879 case ATLBIE:
1880 opset(ASLBIE, r0)
1881 opset(ATLBIEL, r0)
1882
1883 case AEIEIO:
1884 opset(ASLBIA, r0)
1885
1886 case ACMP:
1887 opset(ACMPW, r0)
1888
1889 case ACMPU:
1890 opset(ACMPWU, r0)
1891
1892 case ACMPB:
1893 opset(ACMPB, r0)
1894
1895 case AFTDIV:
1896 opset(AFTDIV, r0)
1897
1898 case AFTSQRT:
1899 opset(AFTSQRT, r0)
1900
1901 case AMOVW:
1902 opset(AMOVWZ, r0)
1903
1904 case AADD,
1905 AADDIS,
1906 AANDCC,
1907 AANDISCC,
1908 AFMOVSX,
1909 AFMOVSZ,
1910 ALSW,
1911 AMOVD,
1912 AMOVB,
1913 AMOVBU,
1914 AMOVFL,
1915
1916 ASUBC,
1917 ASTSW,
1918 ASLBMTE,
1919 AWORD,
1920 ADWORD,
1921 ADARN,
1922 ALDMX,
1923 AVMSUMUDM,
1924 AADDEX,
1925 ACMPEQB,
1926 AECIWX,
1927 ACLRLSLWI,
1928 obj.ANOP,
1929 obj.ATEXT,
1930 obj.AUNDEF,
1931 obj.AFUNCDATA,
1932 obj.APCALIGN,
1933 obj.APCDATA,
1934 obj.ADUFFZERO,
1935 obj.ADUFFCOPY:
1936 break
1937 }
1938 }
1939 }
1940
1941 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
1942 return o<<26 | xo<<1 | oe<<11
1943 }
1944
1945 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
1946 return o<<26 | xo<<2 | oe<<11
1947 }
1948
1949 func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
1950 return o<<26 | xo<<2 | oe<<16
1951 }
1952
1953 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
1954 return o<<26 | xo<<3 | oe<<11
1955 }
1956
1957 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
1958 return o<<26 | xo<<4 | oe<<11
1959 }
1960
1961 func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
1962 return o<<26 | xo | oe<<4
1963 }
1964
1965 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
1966 return o<<26 | xo | oe<<11 | rc&1
1967 }
1968
1969 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
1970 return o<<26 | xo | oe<<11 | (rc&1)<<10
1971 }
1972
1973 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
1974 return o<<26 | xo<<1 | oe<<10 | rc&1
1975 }
1976
1977 func OPCC(o uint32, xo uint32, rc uint32) uint32 {
1978 return OPVCC(o, xo, 0, rc)
1979 }
1980
1981
1982 func OPMD(o, xo, rc uint32) uint32 {
1983 return o<<26 | xo<<2 | rc&1
1984 }
1985
1986
1987 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
1988 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
1989 }
1990
1991
1992 func AOP_RR(op uint32, d uint32, a uint32) uint32 {
1993 return op | (d&31)<<21 | (a&31)<<11
1994 }
1995
1996
1997 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
1998 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
1999 }
2000
2001 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2002 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
2003 }
2004
2005
2006 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2007 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
2008 }
2009
2010
2011 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
2012 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
2013 }
2014
2015
2016 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
2017 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
2018 }
2019
2020
2021 func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
2022 return op | (d&31)<<21 | (simm&31)<<16
2023 }
2024
2025
2026 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 {
2027
2028
2029 r := d - REG_VS0
2030 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
2031 }
2032
2033
2034 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 {
2035 xt := d - REG_VS0
2036 xb := b - REG_VS0
2037 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
2038 }
2039
2040
2041 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 {
2042 xt := d - REG_VS0
2043 xa := a - REG_VS0
2044 xb := b - REG_VS0
2045 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2046 }
2047
2048
2049 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2050 xt := d - REG_VS0
2051 xa := a - REG_VS0
2052 xb := b - REG_VS0
2053 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2054 }
2055
2056
2057 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2058 xt := d - REG_VS0
2059 xa := a - REG_VS0
2060 xb := b - REG_VS0
2061 xc := c - REG_VS0
2062 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2063 }
2064
2065
2066 func AOP_DQ(op uint32, d uint32, a uint32, b uint32) uint32 {
2067
2068
2069 r := d - REG_VS0
2070
2071
2072
2073
2074
2075
2076 dq := b >> 4
2077 return op | (r&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (r&32)>>2
2078 }
2079
2080
2081 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2082 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<9
2083 }
2084
2085
2086 func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2087 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
2088 }
2089
2090 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
2091 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
2092 }
2093
2094 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
2095 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
2096 }
2097
2098 func OP_BR(op uint32, li uint32, aa uint32) uint32 {
2099 return op | li&0x03FFFFFC | aa<<1
2100 }
2101
2102 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
2103 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
2104 }
2105
2106 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
2107 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
2108 }
2109
2110 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
2111 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
2112 }
2113
2114 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
2115 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
2116 }
2117
2118 func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
2119 return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
2120 }
2121
2122 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
2123 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
2124 }
2125
2126 const (
2127
2128 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
2129 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
2130 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
2131 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
2132 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
2133 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
2134 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
2135 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
2136 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
2137 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
2138 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
2139 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
2140 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
2141 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
2142 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
2143 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
2144 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
2145 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
2146 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
2147 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
2148 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
2149 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
2150 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
2151 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
2152 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
2153 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
2154 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
2155 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
2156 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
2157 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
2158 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
2159 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
2160 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
2161 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
2162 OP_EXTSWSLI = 31<<26 | 445<<2
2163 )
2164
2165 func oclass(a *obj.Addr) int {
2166 return int(a.Class) - 1
2167 }
2168
2169 const (
2170 D_FORM = iota
2171 DS_FORM
2172 )
2173
2174
2175
2176
2177
2178
2179
2180
2181 func (c *ctxt9) opform(insn uint32) int {
2182 switch insn {
2183 default:
2184 c.ctxt.Diag("bad insn in loadform: %x", insn)
2185 case OPVCC(58, 0, 0, 0),
2186 OPVCC(58, 0, 0, 1),
2187 OPVCC(58, 0, 0, 0) | 1<<1,
2188 OPVCC(62, 0, 0, 0),
2189 OPVCC(62, 0, 0, 1):
2190 return DS_FORM
2191 case OP_ADDI,
2192 OPVCC(32, 0, 0, 0),
2193 OPVCC(33, 0, 0, 0),
2194 OPVCC(34, 0, 0, 0),
2195 OPVCC(35, 0, 0, 0),
2196 OPVCC(40, 0, 0, 0),
2197 OPVCC(41, 0, 0, 0),
2198 OPVCC(42, 0, 0, 0),
2199 OPVCC(43, 0, 0, 0),
2200 OPVCC(46, 0, 0, 0),
2201 OPVCC(48, 0, 0, 0),
2202 OPVCC(49, 0, 0, 0),
2203 OPVCC(50, 0, 0, 0),
2204 OPVCC(51, 0, 0, 0),
2205 OPVCC(36, 0, 0, 0),
2206 OPVCC(37, 0, 0, 0),
2207 OPVCC(38, 0, 0, 0),
2208 OPVCC(39, 0, 0, 0),
2209 OPVCC(44, 0, 0, 0),
2210 OPVCC(45, 0, 0, 0),
2211 OPVCC(47, 0, 0, 0),
2212 OPVCC(52, 0, 0, 0),
2213 OPVCC(53, 0, 0, 0),
2214 OPVCC(54, 0, 0, 0),
2215 OPVCC(55, 0, 0, 0):
2216 return D_FORM
2217 }
2218 return 0
2219 }
2220
2221
2222
2223 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32) {
2224 if c.ctxt.Headtype == objabi.Haix {
2225
2226 c.ctxt.Diag("symbolAccess called for %s", s.Name)
2227 }
2228 var base uint32
2229 form := c.opform(op)
2230 if c.ctxt.Flag_shared {
2231 base = REG_R2
2232 } else {
2233 base = REG_R0
2234 }
2235
2236
2237 if !reuse {
2238 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
2239 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
2240 } else {
2241 o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
2242 o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
2243 }
2244 rel := obj.Addrel(c.cursym)
2245 rel.Off = int32(c.pc)
2246 rel.Siz = 8
2247 rel.Sym = s
2248 rel.Add = d
2249 if c.ctxt.Flag_shared {
2250 switch form {
2251 case D_FORM:
2252 rel.Type = objabi.R_ADDRPOWER_TOCREL
2253 case DS_FORM:
2254 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
2255 }
2256
2257 } else {
2258 switch form {
2259 case D_FORM:
2260 rel.Type = objabi.R_ADDRPOWER
2261 case DS_FORM:
2262 rel.Type = objabi.R_ADDRPOWER_DS
2263 }
2264 }
2265 return
2266 }
2267
2268
2271 func getmask(m []byte, v uint32) bool {
2272 m[1] = 0
2273 m[0] = m[1]
2274 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 {
2275 if getmask(m, ^v) {
2276 i := int(m[0])
2277 m[0] = m[1] + 1
2278 m[1] = byte(i - 1)
2279 return true
2280 }
2281
2282 return false
2283 }
2284
2285 for i := 0; i < 32; i++ {
2286 if v&(1<<uint(31-i)) != 0 {
2287 m[0] = byte(i)
2288 for {
2289 m[1] = byte(i)
2290 i++
2291 if i >= 32 || v&(1<<uint(31-i)) == 0 {
2292 break
2293 }
2294 }
2295
2296 for ; i < 32; i++ {
2297 if v&(1<<uint(31-i)) != 0 {
2298 return false
2299 }
2300 }
2301 return true
2302 }
2303 }
2304
2305 return false
2306 }
2307
2308 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) {
2309 if !getmask(m, v) {
2310 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p)
2311 }
2312 }
2313
2314
2317 func getmask64(m []byte, v uint64) bool {
2318 m[1] = 0
2319 m[0] = m[1]
2320 for i := 0; i < 64; i++ {
2321 if v&(uint64(1)<<uint(63-i)) != 0 {
2322 m[0] = byte(i)
2323 for {
2324 m[1] = byte(i)
2325 i++
2326 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 {
2327 break
2328 }
2329 }
2330
2331 for ; i < 64; i++ {
2332 if v&(uint64(1)<<uint(63-i)) != 0 {
2333 return false
2334 }
2335 }
2336 return true
2337 }
2338 }
2339
2340 return false
2341 }
2342
2343 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) {
2344 if !getmask64(m, v) {
2345 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p)
2346 }
2347 }
2348
2349 func loadu32(r int, d int64) uint32 {
2350 v := int32(d >> 16)
2351 if isuint32(uint64(d)) {
2352 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
2353 }
2354 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
2355 }
2356
2357 func high16adjusted(d int32) uint16 {
2358 if d&0x8000 != 0 {
2359 return uint16((d >> 16) + 1)
2360 }
2361 return uint16(d >> 16)
2362 }
2363
2364 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
2365 o1 := uint32(0)
2366 o2 := uint32(0)
2367 o3 := uint32(0)
2368 o4 := uint32(0)
2369 o5 := uint32(0)
2370
2371
2372 switch o.type_ {
2373 default:
2374 c.ctxt.Diag("unknown type %d", o.type_)
2375 prasm(p)
2376
2377 case 0:
2378 break
2379
2380 case 2:
2381 r := int(p.Reg)
2382
2383 if r == 0 {
2384 r = int(p.To.Reg)
2385 }
2386 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2387
2388 case 3:
2389 d := c.vregoff(&p.From)
2390
2391 v := int32(d)
2392 r := int(p.From.Reg)
2393 if r == 0 {
2394 r = c.getimpliedreg(&p.From, p)
2395 }
2396 if r0iszero != 0 && p.To.Reg == 0 && (r != 0 || v != 0) {
2397 c.ctxt.Diag("literal operation on R0\n%v", p)
2398 }
2399 a := OP_ADDI
2400 if o.a1 == C_UCON {
2401 if d&0xffff != 0 {
2402 log.Fatalf("invalid handling of %v", p)
2403 }
2404
2405
2406 v >>= 16
2407 if r == REGZERO && isuint32(uint64(d)) {
2408 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v))
2409 break
2410 }
2411
2412 a = OP_ADDIS
2413 } else if int64(int16(d)) != d {
2414
2415 if o.a1 == C_ANDCON {
2416
2417 if r == 0 || r == REGZERO {
2418 o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
2419 break
2420 }
2421
2422 } else if o.a1 != C_ADDCON {
2423 log.Fatalf("invalid handling of %v", p)
2424 }
2425 }
2426
2427 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v))
2428
2429 case 4:
2430 v := c.regoff(&p.From)
2431
2432 r := int(p.Reg)
2433 if r == 0 {
2434 r = int(p.To.Reg)
2435 }
2436 if r0iszero != 0 && p.To.Reg == 0 {
2437 c.ctxt.Diag("literal operation on R0\n%v", p)
2438 }
2439 if int32(int16(v)) != v {
2440 log.Fatalf("mishandled instruction %v", p)
2441 }
2442 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2443
2444 case 5:
2445 o1 = c.oprrr(p.As)
2446
2447 case 6:
2448 r := int(p.Reg)
2449
2450 if r == 0 {
2451 r = int(p.To.Reg)
2452 }
2453
2454 switch p.As {
2455 case AROTL:
2456 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
2457 case AROTLW:
2458 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
2459 default:
2460 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2461 }
2462
2463 case 7:
2464 r := int(p.To.Reg)
2465
2466 if r == 0 {
2467 r = c.getimpliedreg(&p.To, p)
2468 }
2469 v := c.regoff(&p.To)
2470 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 {
2471 if v != 0 {
2472 c.ctxt.Diag("illegal indexed instruction\n%v", p)
2473 }
2474 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
2475 } else {
2476 if int32(int16(v)) != v {
2477 log.Fatalf("mishandled instruction %v", p)
2478 }
2479
2480 inst := c.opstore(p.As)
2481 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2482 log.Fatalf("invalid offset for DS form load/store %v", p)
2483 }
2484 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
2485 }
2486
2487 case 8:
2488 r := int(p.From.Reg)
2489
2490 if r == 0 {
2491 r = c.getimpliedreg(&p.From, p)
2492 }
2493 v := c.regoff(&p.From)
2494 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 {
2495 if v != 0 {
2496 c.ctxt.Diag("illegal indexed instruction\n%v", p)
2497 }
2498 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
2499 } else {
2500 if int32(int16(v)) != v {
2501 log.Fatalf("mishandled instruction %v", p)
2502 }
2503
2504 inst := c.opload(p.As)
2505 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2506 log.Fatalf("invalid offset for DS form load/store %v", p)
2507 }
2508 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
2509 }
2510
2511
2512 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
2513
2514 case 10:
2515 r := int(p.Reg)
2516
2517 if r == 0 {
2518 r = int(p.To.Reg)
2519 }
2520 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
2521
2522 case 11:
2523 v := int32(0)
2524
2525 if p.To.Target() != nil {
2526 v = int32(p.To.Target().Pc - p.Pc)
2527 if v&03 != 0 {
2528 c.ctxt.Diag("odd branch target address\n%v", p)
2529 v &^= 03
2530 }
2531
2532 if v < -(1<<25) || v >= 1<<24 {
2533 c.ctxt.Diag("branch too far\n%v", p)
2534 }
2535 }
2536
2537 o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
2538 if p.To.Sym != nil {
2539 rel := obj.Addrel(c.cursym)
2540 rel.Off = int32(c.pc)
2541 rel.Siz = 4
2542 rel.Sym = p.To.Sym
2543 v += int32(p.To.Offset)
2544 if v&03 != 0 {
2545 c.ctxt.Diag("odd branch target address\n%v", p)
2546 v &^= 03
2547 }
2548
2549 rel.Add = int64(v)
2550 rel.Type = objabi.R_CALLPOWER
2551 }
2552 o2 = 0x60000000
2553
2554 case 13:
2555
2556
2557
2558 if p.From.Type == obj.TYPE_CONST {
2559 o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0)
2560 break
2561 }
2562 if p.To.Type == obj.TYPE_CONST {
2563 c.ctxt.Diag("cannot move into constant 0\n%v", p)
2564 }
2565
2566 switch p.As {
2567 case AMOVB:
2568 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2569 case AMOVBZ:
2570 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
2571 case AMOVH:
2572 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2573 case AMOVHZ:
2574 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
2575 case AMOVW:
2576 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2577 case AMOVWZ:
2578 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5
2579 case AMOVD:
2580 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
2581 default:
2582 c.ctxt.Diag("internal: bad register move/truncation\n%v", p)
2583 }
2584
2585 case 14:
2586 r := int(p.Reg)
2587
2588 if r == 0 {
2589 r = int(p.To.Reg)
2590 }
2591 d := c.vregoff(p.GetFrom3())
2592 var a int
2593 switch p.As {
2594
2595
2596
2597
2598 case ARLDCL, ARLDCLCC:
2599 var mask [2]uint8
2600 c.maskgen64(p, mask[:], uint64(d))
2601
2602 a = int(mask[0])
2603 if mask[1] != 63 {
2604 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
2605 }
2606 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2607 o1 |= (uint32(a) & 31) << 6
2608 if a&0x20 != 0 {
2609 o1 |= 1 << 5
2610 }
2611
2612 case ARLDCR, ARLDCRCC:
2613 var mask [2]uint8
2614 c.maskgen64(p, mask[:], uint64(d))
2615
2616 a = int(mask[1])
2617 if mask[0] != 0 {
2618 c.ctxt.Diag("invalid mask for rotate: %x %x (start != 0)\n%v", uint64(d), mask[0], p)
2619 }
2620 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2621 o1 |= (uint32(a) & 31) << 6
2622 if a&0x20 != 0 {
2623 o1 |= 1 << 5
2624 }
2625
2626
2627 case ARLDICR, ARLDICRCC:
2628 me := int(d)
2629 sh := c.regoff(&p.From)
2630 if me < 0 || me > 63 || sh > 63 {
2631 c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh, p)
2632 }
2633 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me))
2634
2635 case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
2636 mb := int(d)
2637 sh := c.regoff(&p.From)
2638 if mb < 0 || mb > 63 || sh > 63 {
2639 c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh, p)
2640 }
2641 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb))
2642
2643 case ACLRLSLDI:
2644
2645
2646
2647
2648 n := int32(d)
2649 b := c.regoff(&p.From)
2650 if n > b || b > 63 {
2651 c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b, p)
2652 }
2653 o1 = AOP_RLDIC(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
2654
2655 default:
2656 c.ctxt.Diag("unexpected op in rldc case\n%v", p)
2657 a = 0
2658 }
2659
2660 case 17,
2661 16:
2662 a := 0
2663
2664 r := int(p.Reg)
2665
2666 if p.From.Type == obj.TYPE_CONST {
2667 a = int(c.regoff(&p.From))
2668 } else if p.From.Type == obj.TYPE_REG {
2669 if r != 0 {
2670 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
2671 }
2672
2673 switch p.From.Reg {
2674 case REG_CR0:
2675 r = BI_CR0
2676 case REG_CR1:
2677 r = BI_CR1
2678 case REG_CR2:
2679 r = BI_CR2
2680 case REG_CR3:
2681 r = BI_CR3
2682 case REG_CR4:
2683 r = BI_CR4
2684 case REG_CR5:
2685 r = BI_CR5
2686 case REG_CR6:
2687 r = BI_CR6
2688 case REG_CR7:
2689 r = BI_CR7
2690 default:
2691 c.ctxt.Diag("unrecognized register: expecting CR\n")
2692 }
2693 }
2694 v := int32(0)
2695 if p.To.Target() != nil {
2696 v = int32(p.To.Target().Pc - p.Pc)
2697 }
2698 if v&03 != 0 {
2699 c.ctxt.Diag("odd branch target address\n%v", p)
2700 v &^= 03
2701 }
2702
2703 if v < -(1<<16) || v >= 1<<15 {
2704 c.ctxt.Diag("branch too far\n%v", p)
2705 }
2706 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
2707
2708 case 15:
2709 var v int32
2710 if p.As == ABC || p.As == ABCL {
2711 v = c.regoff(&p.To) & 31
2712 } else {
2713 v = 20
2714 }
2715 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11
2716 o2 = OPVCC(19, 16, 0, 0)
2717 if p.As == ABL || p.As == ABCL {
2718 o2 |= 1
2719 }
2720 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index))
2721
2722 case 18:
2723 var v int32
2724 var bh uint32 = 0
2725 if p.As == ABC || p.As == ABCL {
2726 v = c.regoff(&p.From) & 31
2727 } else {
2728 v = 20
2729 }
2730 r := int(p.Reg)
2731 if r == 0 {
2732 r = 0
2733 }
2734 switch oclass(&p.To) {
2735 case C_CTR:
2736 o1 = OPVCC(19, 528, 0, 0)
2737
2738 case C_LR:
2739 o1 = OPVCC(19, 16, 0, 0)
2740
2741 default:
2742 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
2743 v = 0
2744 }
2745
2746
2747 if p.From3Type() != obj.TYPE_NONE {
2748 bh = uint32(p.GetFrom3().Offset)
2749 if bh == 2 || bh > 3 {
2750 log.Fatalf("BH must be 0,1,3 for %v", p)
2751 }
2752 o1 |= bh << 11
2753 }
2754
2755 if p.As == ABL || p.As == ABCL {
2756 o1 |= 1
2757 }
2758 o1 = OP_BCR(o1, uint32(v), uint32(r))
2759
2760 case 19:
2761 d := c.vregoff(&p.From)
2762 o1 = loadu32(int(p.To.Reg), d)
2763 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
2764
2765 case 20:
2766 v := c.regoff(&p.From)
2767
2768 r := int(p.Reg)
2769 if r == 0 {
2770 r = int(p.To.Reg)
2771 }
2772 if p.As == AADD && (r0iszero == 0 && p.Reg == 0 || r0iszero != 0 && p.To.Reg == 0) {
2773 c.ctxt.Diag("literal operation on R0\n%v", p)
2774 }
2775 if p.As == AADDIS {
2776 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2777 } else {
2778 o1 = AOP_IRR(c.opirr(AADDIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
2779 }
2780
2781 case 22:
2782 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2783 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2784 }
2785 d := c.vregoff(&p.From)
2786 r := int(p.Reg)
2787 if r == 0 {
2788 r = int(p.To.Reg)
2789 }
2790 if p.From.Sym != nil {
2791 c.ctxt.Diag("%v is not supported", p)
2792 }
2793
2794
2795 if o.size == 8 {
2796 o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
2797 o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2798 } else {
2799 o1 = loadu32(REGTMP, d)
2800 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d)))
2801 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2802 }
2803
2804 case 23:
2805 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2806 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2807 }
2808 d := c.vregoff(&p.From)
2809 r := int(p.Reg)
2810 if r == 0 {
2811 r = int(p.To.Reg)
2812 }
2813
2814
2815
2816 if o.size == 8 {
2817 o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
2818 o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2819 } else {
2820 o1 = loadu32(REGTMP, d)
2821 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d)))
2822 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2823 }
2824 if p.From.Sym != nil {
2825 c.ctxt.Diag("%v is not supported", p)
2826 }
2827
2828 case 24:
2829 o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
2830
2831 if o.size == 8 {
2832 o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
2833 }
2834
2835 case 25:
2836
2837 v := c.regoff(&p.From)
2838
2839 if v < 0 {
2840 v = 0
2841 } else if v > 63 {
2842 v = 63
2843 }
2844 r := int(p.Reg)
2845 if r == 0 {
2846 r = int(p.To.Reg)
2847 }
2848 var a int
2849 op := uint32(0)
2850 switch p.As {
2851 case ASLD, ASLDCC:
2852 a = int(63 - v)
2853 op = OP_RLDICR
2854
2855 case ASRD, ASRDCC:
2856 a = int(v)
2857 v = 64 - v
2858 op = OP_RLDICL
2859 case AROTL:
2860 a = int(0)
2861 op = OP_RLDICL
2862 case AEXTSWSLI:
2863 a = int(v)
2864 default:
2865 c.ctxt.Diag("unexpected op in sldi case\n%v", p)
2866 a = 0
2867 o1 = 0
2868 }
2869
2870 if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
2871 o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
2872
2873 } else {
2874 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
2875 }
2876 if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
2877 o1 |= 1
2878 }
2879
2880 case 26:
2881 v := c.vregoff(&p.From)
2882 r := int(p.From.Reg)
2883
2884 switch p.From.Name {
2885 case obj.NAME_EXTERN, obj.NAME_STATIC:
2886
2887 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
2888 default:
2889 if r == 0 {
2890 r = c.getimpliedreg(&p.From, p)
2891 }
2892
2893 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
2894 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
2895 }
2896
2897 case 27:
2898 v := c.regoff(p.GetFrom3())
2899
2900 r := int(p.From.Reg)
2901 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2902
2903 case 28:
2904 if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
2905 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2906 }
2907 v := c.regoff(p.GetFrom3())
2908 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
2909 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v))
2910 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
2911 if p.From.Sym != nil {
2912 c.ctxt.Diag("%v is not supported", p)
2913 }
2914
2915 case 29:
2916 v := c.regoff(&p.From)
2917
2918 d := c.vregoff(p.GetFrom3())
2919 var mask [2]uint8
2920 c.maskgen64(p, mask[:], uint64(d))
2921 var a int
2922 switch p.As {
2923 case ARLDC, ARLDCCC:
2924 a = int(mask[0])
2925 if int32(mask[1]) != (63 - v) {
2926 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), mask[1], v, p)
2927 }
2928
2929 case ARLDCL, ARLDCLCC:
2930 a = int(mask[0])
2931 if mask[1] != 63 {
2932 c.ctxt.Diag("invalid mask for shift: %x %s (shift %d)\n%v", uint64(d), mask[1], v, p)
2933 }
2934
2935 case ARLDCR, ARLDCRCC:
2936 a = int(mask[1])
2937 if mask[0] != 0 {
2938 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), mask[0], v, p)
2939 }
2940
2941 default:
2942 c.ctxt.Diag("unexpected op in rldic case\n%v", p)
2943 a = 0
2944 }
2945
2946 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
2947 o1 |= (uint32(a) & 31) << 6
2948 if v&0x20 != 0 {
2949 o1 |= 1 << 1
2950 }
2951 if a&0x20 != 0 {
2952 o1 |= 1 << 5
2953 }
2954
2955 case 30:
2956 v := c.regoff(&p.From)
2957
2958 d := c.vregoff(p.GetFrom3())
2959
2960
2961
2962 switch p.As {
2963 case ARLDMI, ARLDMICC:
2964 var mask [2]uint8
2965 c.maskgen64(p, mask[:], uint64(d))
2966 if int32(mask[1]) != (63 - v) {
2967 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), mask[1], v, p)
2968 }
2969 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
2970 o1 |= (uint32(mask[0]) & 31) << 6
2971 if v&0x20 != 0 {
2972 o1 |= 1 << 1
2973 }
2974 if mask[0]&0x20 != 0 {
2975 o1 |= 1 << 5
2976 }
2977
2978
2979 case ARLDIMI, ARLDIMICC:
2980 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
2981 o1 |= (uint32(d) & 31) << 6
2982 if d&0x20 != 0 {
2983 o1 |= 1 << 5
2984 }
2985 if v&0x20 != 0 {
2986 o1 |= 1 << 1
2987 }
2988 }
2989
2990 case 31:
2991 d := c.vregoff(&p.From)
2992
2993 if c.ctxt.Arch.ByteOrder == binary.BigEndian {
2994 o1 = uint32(d >> 32)
2995 o2 = uint32(d)
2996 } else {
2997 o1 = uint32(d)
2998 o2 = uint32(d >> 32)
2999 }
3000
3001 if p.From.Sym != nil {
3002 rel := obj.Addrel(c.cursym)
3003 rel.Off = int32(c.pc)
3004 rel.Siz = 8
3005 rel.Sym = p.From.Sym
3006 rel.Add = p.From.Offset
3007 rel.Type = objabi.R_ADDR
3008 o2 = 0
3009 o1 = o2
3010 }
3011
3012 case 32:
3013 r := int(p.Reg)
3014
3015 if r == 0 {
3016 r = int(p.To.Reg)
3017 }
3018 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
3019
3020 case 33:
3021 r := int(p.From.Reg)
3022
3023 if oclass(&p.From) == C_NONE {
3024 r = int(p.To.Reg)
3025 }
3026 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
3027
3028 case 34:
3029 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
3030
3031 case 35:
3032 v := c.regoff(&p.To)
3033
3034 r := int(p.To.Reg)
3035 if r == 0 {
3036 r = c.getimpliedreg(&p.To, p)
3037 }
3038
3039 inst := c.opstore(p.As)
3040 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3041 log.Fatalf("invalid offset for DS form load/store %v", p)
3042 }
3043 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3044 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
3045
3046 case 36:
3047 v := c.regoff(&p.From)
3048
3049 r := int(p.From.Reg)
3050 if r == 0 {
3051 r = c.getimpliedreg(&p.From, p)
3052 }
3053 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
3054 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3055
3056
3057 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3058
3059 case 40:
3060 o1 = uint32(c.regoff(&p.From))
3061
3062 case 41:
3063 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3064
3065 case 42:
3066 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3067
3068 case 43:
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079 if p.To.Type == obj.TYPE_NONE {
3080 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
3081 } else {
3082 th := c.regoff(&p.To)
3083 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
3084 }
3085
3086 case 44:
3087 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3088
3089 case 45:
3090 switch p.As {
3091
3092
3093
3094
3095 case ALBAR, ALHAR, ALWAR, ALDAR:
3096 if p.From3Type() != obj.TYPE_NONE {
3097 eh := int(c.regoff(p.GetFrom3()))
3098 if eh > 1 {
3099 c.ctxt.Diag("illegal EH field\n%v", p)
3100 }
3101 o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
3102 } else {
3103 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3104 }
3105 default:
3106 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3107 }
3108 case 46:
3109 o1 = c.oprrr(p.As)
3110
3111 case 47:
3112 r := int(p.From.Reg)
3113
3114 if r == 0 {
3115 r = int(p.To.Reg)
3116 }
3117 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3118
3119 case 48:
3120 r := int(p.From.Reg)
3121
3122 if r == 0 {
3123 r = int(p.To.Reg)
3124 }
3125 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3126
3127 case 49:
3128 if p.From.Type != obj.TYPE_REG {
3129 v := c.regoff(&p.From) & 1
3130 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
3131 } else {
3132 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
3133 }
3134
3135 case 50:
3136 r := int(p.Reg)
3137
3138 if r == 0 {
3139 r = int(p.To.Reg)
3140 }
3141 v := c.oprrr(p.As)
3142 t := v & (1<<10 | 1)
3143 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3144 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
3145 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3146 if p.As == AREMU {
3147 o4 = o3
3148
3149
3150 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
3151 }
3152
3153 case 51:
3154 r := int(p.Reg)
3155
3156 if r == 0 {
3157 r = int(p.To.Reg)
3158 }
3159 v := c.oprrr(p.As)
3160 t := v & (1<<10 | 1)
3161 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3162 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
3163 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3164
3165
3166
3167
3168 case 52:
3169 v := c.regoff(&p.From) & 31
3170
3171 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
3172
3173 case 53:
3174 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
3175
3176 case 55:
3177 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
3178
3179 case 56:
3180 v := c.regoff(&p.From)
3181
3182 r := int(p.Reg)
3183 if r == 0 {
3184 r = int(p.To.Reg)
3185 }
3186 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
3187 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
3188 o1 |= 1 << 1
3189 }
3190
3191 case 57:
3192 v := c.regoff(&p.From)
3193
3194 r := int(p.Reg)
3195 if r == 0 {
3196 r = int(p.To.Reg)
3197 }
3198
3199
3206 if v < 0 {
3207 v = 0
3208 } else if v > 32 {
3209 v = 32
3210 }
3211 var mask [2]uint8
3212 switch p.As {
3213 case AROTLW:
3214 mask[0], mask[1] = 0, 31
3215 case ASRW, ASRWCC:
3216 mask[0], mask[1] = uint8(v), 31
3217 v = 32 - v
3218 default:
3219 mask[0], mask[1] = 0, uint8(31-v)
3220 }
3221 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
3222 if p.As == ASLWCC || p.As == ASRWCC {
3223 o1 |= 1
3224 }
3225
3226 case 58:
3227 v := c.regoff(&p.From)
3228
3229 r := int(p.Reg)
3230 if r == 0 {
3231 r = int(p.To.Reg)
3232 }
3233 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3234
3235 case 59:
3236 v := c.regoff(&p.From)
3237
3238 r := int(p.Reg)
3239 if r == 0 {
3240 r = int(p.To.Reg)
3241 }
3242 switch p.As {
3243 case AOR:
3244 o1 = LOP_IRR(c.opirr(AORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
3245 case AXOR:
3246 o1 = LOP_IRR(c.opirr(AXORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
3247 case AANDCC:
3248 o1 = LOP_IRR(c.opirr(AANDISCC), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
3249 default:
3250 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3251 }
3252
3253 case 60:
3254 r := int(c.regoff(&p.From) & 31)
3255
3256 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
3257
3258 case 61:
3259 r := int(c.regoff(&p.From) & 31)
3260
3261 v := c.regoff(&p.To)
3262 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
3263
3264 case 62:
3265 v := c.regoff(&p.From)
3266 switch p.As {
3267 case ACLRLSLWI:
3268 n := c.regoff(p.GetFrom3())
3269
3270
3271
3272 if n > v || v >= 32 {
3273 c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p)
3274 }
3275
3276 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n))
3277 default:
3278 var mask [2]uint8
3279 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
3280 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v))
3281 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
3282 }
3283
3284 case 63:
3285 var mask [2]uint8
3286 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
3287 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg))
3288 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
3289
3290 case 64:
3291 var v int32
3292 if p.From3Type() != obj.TYPE_NONE {
3293 v = c.regoff(p.GetFrom3()) & 255
3294 } else {
3295 v = 255
3296 }
3297 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
3298
3299 case 65:
3300 if p.To.Reg == 0 {
3301 c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
3302 }
3303 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
3304
3305 case 66:
3306 var r int
3307 var v int32
3308 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
3309 r = int(p.From.Reg)
3310 v = int32(p.To.Reg)
3311 if REG_DCR0 <= v && v <= REG_DCR0+1023 {
3312 o1 = OPVCC(31, 451, 0, 0)
3313 } else {
3314 o1 = OPVCC(31, 467, 0, 0)
3315 }
3316 } else {
3317 r = int(p.To.Reg)
3318 v = int32(p.From.Reg)
3319 if REG_DCR0 <= v && v <= REG_DCR0+1023 {
3320 o1 = OPVCC(31, 323, 0, 0)
3321 } else {
3322 o1 = OPVCC(31, 339, 0, 0)
3323 }
3324 }
3325
3326 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3327
3328 case 67:
3329 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3330 c.ctxt.Diag("illegal CR field number\n%v", p)
3331 }
3332 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
3333
3334 case 68:
3335 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 {
3336 v := int32(1 << uint(7-(p.To.Reg&7)))
3337 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12
3338 } else {
3339 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0)
3340 }
3341
3342 case 69:
3343 var v int32
3344 if p.From3Type() != obj.TYPE_NONE {
3345 if p.To.Reg != 0 {
3346 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p)
3347 }
3348 v = c.regoff(p.GetFrom3()) & 0xff
3349 } else {
3350 if p.To.Reg == 0 {
3351 v = 0xff
3352 } else {
3353 v = 1 << uint(7-(p.To.Reg&7))
3354 }
3355 }
3356
3357 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
3358
3359 case 70:
3360 var r int
3361 if p.Reg == 0 {
3362 r = 0
3363 } else {
3364 r = (int(p.Reg) & 7) << 2
3365 }
3366 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg))
3367
3368 case 71:
3369 var r int
3370 if p.Reg == 0 {
3371 r = 0
3372 } else {
3373 r = (int(p.Reg) & 7) << 2
3374 }
3375 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff
3376
3377 case 72:
3378 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
3379
3380 case 73:
3381 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3382 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
3383 }
3384 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
3385
3386 case 77:
3387 if p.From.Type == obj.TYPE_CONST {
3388 if p.From.Offset > BIG || p.From.Offset < -BIG {
3389 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
3390 }
3391 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
3392 } else if p.From.Type == obj.TYPE_REG {
3393 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
3394 } else {
3395 c.ctxt.Diag("illegal syscall: %v", p)
3396 o1 = 0x7fe00008
3397 }
3398
3399 o2 = c.oprrr(p.As)
3400 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO)
3401
3402 case 78:
3403 o1 = 0
3405
3406
3407 case 74:
3408 v := c.vregoff(&p.To)
3409
3410 inst := c.opstore(p.As)
3411 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3412 log.Fatalf("invalid offset for DS form load/store %v", p)
3413 }
3414
3415 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
3416
3417 case 75:
3418 v := p.From.Offset
3419
3420
3421 inst := c.opload(p.As)
3422 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3423 log.Fatalf("invalid offset for DS form load/store %v", p)
3424 }
3425 switch p.From.Name {
3426 case obj.NAME_GOTREF, obj.NAME_TOCREF:
3427 if v != 0 {
3428 c.ctxt.Diag("invalid offset for GOT/TOC access %v", p)
3429 }
3430 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3431 o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3432 rel := obj.Addrel(c.cursym)
3433 rel.Off = int32(c.pc)
3434 rel.Siz = 8
3435 rel.Sym = p.From.Sym
3436 switch p.From.Name {
3437 case obj.NAME_GOTREF:
3438 rel.Type = objabi.R_ADDRPOWER_GOT
3439 case obj.NAME_TOCREF:
3440 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
3441 }
3442 default:
3443 reuseBaseReg := p.As != AFMOVD && p.As != AFMOVS
3444
3445 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
3446 }
3447
3448 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3449
3450 case 79:
3451 if p.From.Offset != 0 {
3452 c.ctxt.Diag("invalid offset against tls var %v", p)
3453 }
3454 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R13, 0)
3455 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3456 rel := obj.Addrel(c.cursym)
3457 rel.Off = int32(c.pc)
3458 rel.Siz = 8
3459 rel.Sym = p.From.Sym
3460 rel.Type = objabi.R_POWER_TLS_LE
3461
3462 case 80:
3463 if p.From.Offset != 0 {
3464 c.ctxt.Diag("invalid offset against tls var %v", p)
3465 }
3466 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3467 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
3468 o3 = AOP_RRR(OP_ADD, uint32(p.To.Reg), uint32(p.To.Reg), REG_R13)
3469 rel := obj.Addrel(c.cursym)
3470 rel.Off = int32(c.pc)
3471 rel.Siz = 8
3472 rel.Sym = p.From.Sym
3473 rel.Type = objabi.R_POWER_TLS_IE
3474 rel = obj.Addrel(c.cursym)
3475 rel.Off = int32(c.pc) + 8
3476 rel.Siz = 4
3477 rel.Sym = p.From.Sym
3478 rel.Type = objabi.R_POWER_TLS
3479
3480 case 82:
3481 if p.From.Type == obj.TYPE_REG {
3482
3483
3484
3485 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3486 } else if p.From3Type() == obj.TYPE_CONST {
3487
3488
3489 six := int(c.regoff(&p.From))
3490 st := int(c.regoff(p.GetFrom3()))
3491 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
3492 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
3493
3494
3495 uim := int(c.regoff(&p.From))
3496 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
3497 } else {
3498
3499
3500 sim := int(c.regoff(&p.From))
3501 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
3502 }
3503
3504 case 83:
3505 if p.From.Type == obj.TYPE_REG {
3506
3507
3508 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3509 } else if p.From.Type == obj.TYPE_CONST {
3510
3511
3512 shb := int(c.regoff(&p.From))
3513 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
3514 }
3515
3516 case 84:
3517 bc := c.vregoff(&p.From)
3518
3519
3520 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
3521
3522 case 85:
3523
3524
3525 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
3526
3527 case 86:
3528
3529
3530 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3531
3532 case 87:
3533
3534
3535 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3536
3537 case 88:
3538
3539
3540
3541 xt := int32(p.To.Reg)
3542 xs := int32(p.From.Reg)
3543
3544 if REG_V0 <= xt && xt <= REG_V31 {
3545
3546 xt = xt + 64
3547 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
3548 } else if REG_F0 <= xt && xt <= REG_F31 {
3549
3550 xt = xt + 64
3551 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
3552 } else if REG_VS0 <= xt && xt <= REG_VS63 {
3553 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
3554 } else if REG_V0 <= xs && xs <= REG_V31 {
3555
3556 xs = xs + 64
3557 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
3558 } else if REG_F0 <= xs && xs <= REG_F31 {
3559 xs = xs + 64
3560 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
3561 } else if REG_VS0 <= xs && xs <= REG_VS63 {
3562 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
3563 }
3564
3565 case 89:
3566
3567
3568 uim := int(c.regoff(p.GetFrom3()))
3569 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
3570
3571 case 90:
3572 if p.From3Type() == obj.TYPE_NONE {
3573
3574
3575 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3576 } else if p.From3Type() == obj.TYPE_CONST {
3577
3578
3579 dm := int(c.regoff(p.GetFrom3()))
3580 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
3581 }
3582
3583 case 91:
3584
3585
3586 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3587
3588 case 92:
3589 if p.To.Type == obj.TYPE_CONST {
3590
3591 xf := int32(p.From.Reg)
3592 if REG_F0 <= xf && xf <= REG_F31 {
3593
3594 bf := int(c.regoff(&p.To)) << 2
3595 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3596 } else {
3597
3598 l := int(c.regoff(&p.To))
3599 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
3600 }
3601 } else if p.From3Type() == obj.TYPE_CONST {
3602
3603
3604 l := int(c.regoff(p.GetFrom3()))
3605 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
3606 } else if p.To.Type == obj.TYPE_REG {
3607 cr := int32(p.To.Reg)
3608 if REG_CR0 <= cr && cr <= REG_CR7 {
3609
3610
3611 bf := (int(p.To.Reg) & 7) << 2
3612 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3613 } else if p.From.Type == obj.TYPE_CONST {
3614
3615
3616 l := int(c.regoff(&p.From))
3617 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
3618 } else {
3619 switch p.As {
3620 case ACOPY, APASTECC:
3621 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
3622 default:
3623
3624
3625 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3626 }
3627 }
3628 }
3629
3630 case 93:
3631 if p.To.Type == obj.TYPE_CONST {
3632
3633
3634 bf := int(c.regoff(&p.To)) << 2
3635 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
3636 } else if p.Reg == 0 {
3637
3638
3639 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3640 }
3641
3642 case 94:
3643
3644
3645 cy := int(c.regoff(p.GetFrom3()))
3646 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
3647
3648 case 96:
3649
3650
3651 dq := int16(c.regoff(&p.From))
3652 if (dq & 15) != 0 {
3653 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3654 }
3655 o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
3656
3657 case 97:
3658
3659
3660 dq := int16(c.regoff(&p.To))
3661 if (dq & 15) != 0 {
3662 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3663 }
3664 o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
3665 case 98:
3666
3667 o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3668 case 99:
3669
3670 o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
3671 case 100:
3672 if p.From.Type == obj.TYPE_CONST {
3673
3674 uim := int(c.regoff(&p.From))
3675
3676
3677 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
3678 } else {
3679 c.ctxt.Diag("invalid ops for %v", p.As)
3680 }
3681 case 101:
3682 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
3683
3684 case 102:
3685 mb := uint32(c.regoff(&p.RestArgs[0].Addr))
3686 me := uint32(c.regoff(&p.RestArgs[1].Addr))
3687 sh := uint32(c.regoff(&p.From))
3688 o1 = OP_RLW(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, mb, me)
3689
3690 case 103:
3691 mb := uint32(c.regoff(&p.RestArgs[0].Addr))
3692 me := uint32(c.regoff(&p.RestArgs[1].Addr))
3693 o1 = OP_RLW(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), mb, me)
3694 }
3695
3696 out[0] = o1
3697 out[1] = o2
3698 out[2] = o3
3699 out[3] = o4
3700 out[4] = o5
3701 }
3702
3703 func (c *ctxt9) vregoff(a *obj.Addr) int64 {
3704 c.instoffset = 0
3705 if a != nil {
3706 c.aclass(a)
3707 }
3708 return c.instoffset
3709 }
3710
3711 func (c *ctxt9) regoff(a *obj.Addr) int32 {
3712 return int32(c.vregoff(a))
3713 }
3714
3715 func (c *ctxt9) oprrr(a obj.As) uint32 {
3716 switch a {
3717 case AADD:
3718 return OPVCC(31, 266, 0, 0)
3719 case AADDCC:
3720 return OPVCC(31, 266, 0, 1)
3721 case AADDV:
3722 return OPVCC(31, 266, 1, 0)
3723 case AADDVCC:
3724 return OPVCC(31, 266, 1, 1)
3725 case AADDC:
3726 return OPVCC(31, 10, 0, 0)
3727 case AADDCCC:
3728 return OPVCC(31, 10, 0, 1)
3729 case AADDCV:
3730 return OPVCC(31, 10, 1, 0)
3731 case AADDCVCC:
3732 return OPVCC(31, 10, 1, 1)
3733 case AADDE:
3734 return OPVCC(31, 138, 0, 0)
3735 case AADDECC:
3736 return OPVCC(31, 138, 0, 1)
3737 case AADDEV:
3738 return OPVCC(31, 138, 1, 0)
3739 case AADDEVCC:
3740 return OPVCC(31, 138, 1, 1)
3741 case AADDME:
3742 return OPVCC(31, 234, 0, 0)
3743 case AADDMECC:
3744 return OPVCC(31, 234, 0, 1)
3745 case AADDMEV:
3746 return OPVCC(31, 234, 1, 0)
3747 case AADDMEVCC:
3748 return OPVCC(31, 234, 1, 1)
3749 case AADDZE:
3750 return OPVCC(31, 202, 0, 0)
3751 case AADDZECC:
3752 return OPVCC(31, 202, 0, 1)
3753 case AADDZEV:
3754 return OPVCC(31, 202, 1, 0)
3755 case AADDZEVCC:
3756 return OPVCC(31, 202, 1, 1)
3757 case AADDEX:
3758 return OPVCC(31, 170, 0, 0)
3759
3760 case AAND:
3761 return OPVCC(31, 28, 0, 0)
3762 case AANDCC:
3763 return OPVCC(31, 28, 0, 1)
3764 case AANDN:
3765 return OPVCC(31, 60, 0, 0)
3766 case AANDNCC:
3767 return OPVCC(31, 60, 0, 1)
3768
3769 case ACMP:
3770 return OPVCC(31, 0, 0, 0) | 1<<21
3771 case ACMPU:
3772 return OPVCC(31, 32, 0, 0) | 1<<21
3773 case ACMPW:
3774 return OPVCC(31, 0, 0, 0)
3775 case ACMPWU:
3776 return OPVCC(31, 32, 0, 0)
3777 case ACMPB:
3778 return OPVCC(31, 508, 0, 0)
3779 case ACMPEQB:
3780 return OPVCC(31, 224, 0, 0)
3781
3782 case ACNTLZW:
3783 return OPVCC(31, 26, 0, 0)
3784 case ACNTLZWCC:
3785 return OPVCC(31, 26, 0, 1)
3786 case ACNTLZD:
3787 return OPVCC(31, 58, 0, 0)
3788 case ACNTLZDCC:
3789 return OPVCC(31, 58, 0, 1)
3790
3791 case ACRAND:
3792 return OPVCC(19, 257, 0, 0)
3793 case ACRANDN:
3794 return OPVCC(19, 129, 0, 0)
3795 case ACREQV:
3796 return OPVCC(19, 289, 0, 0)
3797 case ACRNAND:
3798 return OPVCC(19, 225, 0, 0)
3799 case ACRNOR:
3800 return OPVCC(19, 33, 0, 0)
3801 case ACROR:
3802 return OPVCC(19, 449, 0, 0)
3803 case ACRORN:
3804 return OPVCC(19, 417, 0, 0)
3805 case ACRXOR:
3806 return OPVCC(19, 193, 0, 0)
3807
3808 case ADCBF:
3809 return OPVCC(31, 86, 0, 0)
3810 case ADCBI:
3811 return OPVCC(31, 470, 0, 0)
3812 case ADCBST:
3813 return OPVCC(31, 54, 0, 0)
3814 case ADCBT:
3815 return OPVCC(31, 278, 0, 0)
3816 case ADCBTST:
3817 return OPVCC(31, 246, 0, 0)
3818 case ADCBZ:
3819 return OPVCC(31, 1014, 0, 0)
3820
3821 case AMODUD:
3822 return OPVCC(31, 265, 0, 0)
3823 case AMODUW:
3824 return OPVCC(31, 267, 0, 0)
3825 case AMODSD:
3826 return OPVCC(31, 777, 0, 0)
3827 case AMODSW:
3828 return OPVCC(31, 779, 0, 0)
3829
3830 case ADIVW, AREM:
3831 return OPVCC(31, 491, 0, 0)
3832
3833 case ADIVWCC:
3834 return OPVCC(31, 491, 0, 1)
3835
3836 case ADIVWV:
3837 return OPVCC(31, 491, 1, 0)
3838
3839 case ADIVWVCC:
3840 return OPVCC(31, 491, 1, 1)
3841
3842 case ADIVWU, AREMU:
3843 return OPVCC(31, 459, 0, 0)
3844
3845 case ADIVWUCC:
3846 return OPVCC(31, 459, 0, 1)
3847
3848 case ADIVWUV:
3849 return OPVCC(31, 459, 1, 0)
3850
3851 case ADIVWUVCC:
3852 return OPVCC(31, 459, 1, 1)
3853
3854 case ADIVD, AREMD:
3855 return OPVCC(31, 489, 0, 0)
3856
3857 case ADIVDCC:
3858 return OPVCC(31, 489, 0, 1)
3859
3860 case ADIVDE:
3861 return OPVCC(31, 425, 0, 0)
3862
3863 case ADIVDECC:
3864 return OPVCC(31, 425, 0, 1)
3865
3866 case ADIVDEU:
3867 return OPVCC(31, 393, 0, 0)
3868
3869 case ADIVDEUCC:
3870 return OPVCC(31, 393, 0, 1)
3871
3872 case ADIVDV:
3873 return OPVCC(31, 489, 1, 0)
3874
3875 case ADIVDVCC:
3876 return OPVCC(31, 489, 1, 1)
3877
3878 case ADIVDU, AREMDU:
3879 return OPVCC(31, 457, 0, 0)
3880
3881 case ADIVDUCC:
3882 return OPVCC(31, 457, 0, 1)
3883
3884 case ADIVDUV:
3885 return OPVCC(31, 457, 1, 0)
3886
3887 case ADIVDUVCC:
3888 return OPVCC(31, 457, 1, 1)
3889
3890 case AEIEIO:
3891 return OPVCC(31, 854, 0, 0)
3892
3893 case AEQV:
3894 return OPVCC(31, 284, 0, 0)
3895 case AEQVCC:
3896 return OPVCC(31, 284, 0, 1)
3897
3898 case AEXTSB:
3899 return OPVCC(31, 954, 0, 0)
3900 case AEXTSBCC:
3901 return OPVCC(31, 954, 0, 1)
3902 case AEXTSH:
3903 return OPVCC(31, 922, 0, 0)
3904 case AEXTSHCC:
3905 return OPVCC(31, 922, 0, 1)
3906 case AEXTSW:
3907 return OPVCC(31, 986, 0, 0)
3908 case AEXTSWCC:
3909 return OPVCC(31, 986, 0, 1)
3910
3911 case AFABS:
3912 return OPVCC(63, 264, 0, 0)
3913 case AFABSCC:
3914 return OPVCC(63, 264, 0, 1)
3915 case AFADD:
3916 return OPVCC(63, 21, 0, 0)
3917 case AFADDCC:
3918 return OPVCC(63, 21, 0, 1)
3919 case AFADDS:
3920 return OPVCC(59, 21, 0, 0)
3921 case AFADDSCC:
3922 return OPVCC(59, 21, 0, 1)
3923 case AFCMPO:
3924 return OPVCC(63, 32, 0, 0)
3925 case AFCMPU:
3926 return OPVCC(63, 0, 0, 0)
3927 case AFCFID:
3928 return OPVCC(63, 846, 0, 0)
3929 case AFCFIDCC:
3930 return OPVCC(63, 846, 0, 1)
3931 case AFCFIDU:
3932 return OPVCC(63, 974, 0, 0)
3933 case AFCFIDUCC:
3934 return OPVCC(63, 974, 0, 1)
3935 case AFCFIDS:
3936 return OPVCC(59, 846, 0, 0)
3937 case AFCFIDSCC:
3938 return OPVCC(59, 846, 0, 1)
3939 case AFCTIW:
3940 return OPVCC(63, 14, 0, 0)
3941 case AFCTIWCC:
3942 return OPVCC(63, 14, 0, 1)
3943 case AFCTIWZ:
3944 return OPVCC(63, 15, 0, 0)
3945 case AFCTIWZCC:
3946 return OPVCC(63, 15, 0, 1)
3947 case AFCTID:
3948 return OPVCC(63, 814, 0, 0)
3949 case AFCTIDCC:
3950 return OPVCC(63, 814, 0, 1)
3951 case AFCTIDZ:
3952 return OPVCC(63, 815, 0, 0)
3953 case AFCTIDZCC:
3954 return OPVCC(63, 815, 0, 1)
3955 case AFDIV:
3956 return OPVCC(63, 18, 0, 0)
3957 case AFDIVCC:
3958 return OPVCC(63, 18, 0, 1)
3959 case AFDIVS:
3960 return OPVCC(59, 18, 0, 0)
3961 case AFDIVSCC:
3962 return OPVCC(59, 18, 0, 1)
3963 case AFMADD:
3964 return OPVCC(63, 29, 0, 0)
3965 case AFMADDCC:
3966 return OPVCC(63, 29, 0, 1)
3967 case AFMADDS:
3968 return OPVCC(59, 29, 0, 0)
3969 case AFMADDSCC:
3970 return OPVCC(59, 29, 0, 1)
3971
3972 case AFMOVS, AFMOVD:
3973 return OPVCC(63, 72, 0, 0)
3974 case AFMOVDCC:
3975 return OPVCC(63, 72, 0, 1)
3976 case AFMSUB:
3977 return OPVCC(63, 28, 0, 0)
3978 case AFMSUBCC:
3979 return OPVCC(63, 28, 0, 1)
3980 case AFMSUBS:
3981 return OPVCC(59, 28, 0, 0)
3982 case AFMSUBSCC:
3983 return OPVCC(59, 28, 0, 1)
3984 case AFMUL:
3985 return OPVCC(63, 25, 0, 0)
3986 case AFMULCC:
3987 return OPVCC(63, 25, 0, 1)
3988 case AFMULS:
3989 return OPVCC(59, 25, 0, 0)
3990 case AFMULSCC:
3991 return OPVCC(59, 25, 0, 1)
3992 case AFNABS:
3993 return OPVCC(63, 136, 0, 0)
3994 case AFNABSCC:
3995 return OPVCC(63, 136, 0, 1)
3996 case AFNEG:
3997 return OPVCC(63, 40, 0, 0)
3998 case AFNEGCC:
3999 return OPVCC(63, 40, 0, 1)
4000 case AFNMADD:
4001 return OPVCC(63, 31, 0, 0)
4002 case AFNMADDCC:
4003 return OPVCC(63, 31, 0, 1)
4004 case AFNMADDS:
4005 return OPVCC(59, 31, 0, 0)
4006 case AFNMADDSCC:
4007 return OPVCC(59, 31, 0, 1)
4008 case AFNMSUB:
4009 return OPVCC(63, 30, 0, 0)
4010 case AFNMSUBCC:
4011 return OPVCC(63, 30, 0, 1)
4012 case AFNMSUBS:
4013 return OPVCC(59, 30, 0, 0)
4014 case AFNMSUBSCC:
4015 return OPVCC(59, 30, 0, 1)
4016 case AFCPSGN:
4017 return OPVCC(63, 8, 0, 0)
4018 case AFCPSGNCC:
4019 return OPVCC(63, 8, 0, 1)
4020 case AFRES:
4021 return OPVCC(59, 24, 0, 0)
4022 case AFRESCC:
4023 return OPVCC(59, 24, 0, 1)
4024 case AFRIM:
4025 return OPVCC(63, 488, 0, 0)
4026 case AFRIMCC:
4027 return OPVCC(63, 488, 0, 1)
4028 case AFRIP:
4029 return OPVCC(63, 456, 0, 0)
4030 case AFRIPCC:
4031 return OPVCC(63, 456, 0, 1)
4032 case AFRIZ:
4033 return OPVCC(63, 424, 0, 0)
4034 case AFRIZCC:
4035 return OPVCC(63, 424, 0, 1)
4036 case AFRIN:
4037 return OPVCC(63, 392, 0, 0)
4038 case AFRINCC:
4039 return OPVCC(63, 392, 0, 1)
4040 case AFRSP:
4041 return OPVCC(63, 12, 0, 0)
4042 case AFRSPCC:
4043 return OPVCC(63, 12, 0, 1)
4044 case AFRSQRTE:
4045 return OPVCC(63, 26, 0, 0)
4046 case AFRSQRTECC:
4047 return OPVCC(63, 26, 0, 1)
4048 case AFSEL:
4049 return OPVCC(63, 23, 0, 0)
4050 case AFSELCC:
4051 return OPVCC(63, 23, 0, 1)
4052 case AFSQRT:
4053 return OPVCC(63, 22, 0, 0)
4054 case AFSQRTCC:
4055 return OPVCC(63, 22, 0, 1)
4056 case AFSQRTS:
4057 return OPVCC(59, 22, 0, 0)
4058 case AFSQRTSCC:
4059 return OPVCC(59, 22, 0, 1)
4060 case AFSUB:
4061 return OPVCC(63, 20, 0, 0)
4062 case AFSUBCC:
4063 return OPVCC(63, 20, 0, 1)
4064 case AFSUBS:
4065 return OPVCC(59, 20, 0, 0)
4066 case AFSUBSCC:
4067 return OPVCC(59, 20, 0, 1)
4068
4069 case AICBI:
4070 return OPVCC(31, 982, 0, 0)
4071 case AISYNC:
4072 return OPVCC(19, 150, 0, 0)
4073
4074 case AMTFSB0:
4075 return OPVCC(63, 70, 0, 0)
4076 case AMTFSB0CC:
4077 return OPVCC(63, 70, 0, 1)
4078 case AMTFSB1:
4079 return OPVCC(63, 38, 0, 0)
4080 case AMTFSB1CC:
4081 return OPVCC(63, 38, 0, 1)
4082
4083 case AMULHW:
4084 return OPVCC(31, 75, 0, 0)
4085 case AMULHWCC:
4086 return OPVCC(31, 75, 0, 1)
4087 case AMULHWU:
4088 return OPVCC(31, 11, 0, 0)
4089 case AMULHWUCC:
4090 return OPVCC(31, 11, 0, 1)
4091 case AMULLW:
4092 return OPVCC(31, 235, 0, 0)
4093 case AMULLWCC:
4094 return OPVCC(31, 235, 0, 1)
4095 case AMULLWV:
4096 return OPVCC(31, 235, 1, 0)
4097 case AMULLWVCC:
4098 return OPVCC(31, 235, 1, 1)
4099
4100 case AMULHD:
4101 return OPVCC(31, 73, 0, 0)
4102 case AMULHDCC:
4103 return OPVCC(31, 73, 0, 1)
4104 case AMULHDU:
4105 return OPVCC(31, 9, 0, 0)
4106 case AMULHDUCC:
4107 return OPVCC(31, 9, 0, 1)
4108 case AMULLD:
4109 return OPVCC(31, 233, 0, 0)
4110 case AMULLDCC:
4111 return OPVCC(31, 233, 0, 1)
4112 case AMULLDV:
4113 return OPVCC(31, 233, 1, 0)
4114 case AMULLDVCC:
4115 return OPVCC(31, 233, 1, 1)
4116
4117 case ANAND:
4118 return OPVCC(31, 476, 0, 0)
4119 case ANANDCC:
4120 return OPVCC(31, 476, 0, 1)
4121 case ANEG:
4122 return OPVCC(31, 104, 0, 0)
4123 case ANEGCC:
4124 return OPVCC(31, 104, 0, 1)
4125 case ANEGV:
4126 return OPVCC(31, 104, 1, 0)
4127 case ANEGVCC:
4128 return OPVCC(31, 104, 1, 1)
4129 case ANOR:
4130 return OPVCC(31, 124, 0, 0)
4131 case ANORCC:
4132 return OPVCC(31, 124, 0, 1)
4133 case AOR:
4134 return OPVCC(31, 444, 0, 0)
4135 case AORCC:
4136 return OPVCC(31, 444, 0, 1)
4137 case AORN:
4138 return OPVCC(31, 412, 0, 0)
4139 case AORNCC:
4140 return OPVCC(31, 412, 0, 1)
4141
4142 case APOPCNTD:
4143 return OPVCC(31, 506, 0, 0)
4144 case APOPCNTW:
4145 return OPVCC(31, 378, 0, 0)
4146 case APOPCNTB:
4147 return OPVCC(31, 122, 0, 0)
4148 case ACNTTZW:
4149 return OPVCC(31, 538, 0, 0)
4150 case ACNTTZWCC:
4151 return OPVCC(31, 538, 0, 1)
4152 case ACNTTZD:
4153 return OPVCC(31, 570, 0, 0)
4154 case ACNTTZDCC:
4155 return OPVCC(31, 570, 0, 1)
4156
4157 case ARFI:
4158 return OPVCC(19, 50, 0, 0)
4159 case ARFCI:
4160 return OPVCC(19, 51, 0, 0)
4161 case ARFID:
4162 return OPVCC(19, 18, 0, 0)
4163 case AHRFID:
4164 return OPVCC(19, 274, 0, 0)
4165
4166 case ARLWMI:
4167 return OPVCC(20, 0, 0, 0)
4168 case ARLWMICC:
4169 return OPVCC(20, 0, 0, 1)
4170 case ARLWNM:
4171 return OPVCC(23, 0, 0, 0)
4172 case ARLWNMCC:
4173 return OPVCC(23, 0, 0, 1)
4174
4175 case ARLDCL:
4176 return OPVCC(30, 8, 0, 0)
4177 case ARLDCLCC:
4178 return OPVCC(30, 0, 0, 1)
4179
4180 case ARLDCR:
4181 return OPVCC(30, 9, 0, 0)
4182 case ARLDCRCC:
4183 return OPVCC(30, 9, 0, 1)
4184
4185 case ARLDICL:
4186 return OPVCC(30, 0, 0, 0)
4187 case ARLDICLCC:
4188 return OPVCC(30, 0, 0, 1)
4189 case ARLDICR:
4190 return OPMD(30, 1, 0)
4191 case ARLDICRCC:
4192 return OPMD(30, 1, 1)
4193
4194 case ARLDIC:
4195 return OPMD(30, 2, 0)
4196 case ARLDICCC:
4197 return OPMD(30, 2, 1)
4198
4199 case ASYSCALL:
4200 return OPVCC(17, 1, 0, 0)
4201
4202 case ASLW:
4203 return OPVCC(31, 24, 0, 0)
4204 case ASLWCC:
4205 return OPVCC(31, 24, 0, 1)
4206 case ASLD:
4207 return OPVCC(31, 27, 0, 0)
4208 case ASLDCC:
4209 return OPVCC(31, 27, 0, 1)
4210
4211 case ASRAW:
4212 return OPVCC(31, 792, 0, 0)
4213 case ASRAWCC:
4214 return OPVCC(31, 792, 0, 1)
4215 case ASRAD:
4216 return OPVCC(31, 794, 0, 0)
4217 case ASRADCC:
4218 return OPVCC(31, 794, 0, 1)
4219
4220 case AEXTSWSLI:
4221 return OPVCC(31, 445, 0, 0)
4222 case AEXTSWSLICC:
4223 return OPVCC(31, 445, 0, 1)
4224
4225 case ASRW:
4226 return OPVCC(31, 536, 0, 0)
4227 case ASRWCC:
4228 return OPVCC(31, 536, 0, 1)
4229 case ASRD:
4230 return OPVCC(31, 539, 0, 0)
4231 case ASRDCC:
4232 return OPVCC(31, 539, 0, 1)
4233
4234 case ASUB:
4235 return OPVCC(31, 40, 0, 0)
4236 case ASUBCC:
4237 return OPVCC(31, 40, 0, 1)
4238 case ASUBV:
4239 return OPVCC(31, 40, 1, 0)
4240 case ASUBVCC:
4241 return OPVCC(31, 40, 1, 1)
4242 case ASUBC:
4243 return OPVCC(31, 8, 0, 0)
4244 case ASUBCCC:
4245 return OPVCC(31, 8, 0, 1)
4246 case ASUBCV:
4247 return OPVCC(31, 8, 1, 0)
4248 case ASUBCVCC:
4249 return OPVCC(31, 8, 1, 1)
4250 case ASUBE:
4251 return OPVCC(31, 136, 0, 0)
4252 case ASUBECC:
4253 return OPVCC(31, 136, 0, 1)
4254 case ASUBEV:
4255 return OPVCC(31, 136, 1, 0)
4256 case ASUBEVCC:
4257 return OPVCC(31, 136, 1, 1)
4258 case ASUBME:
4259 return OPVCC(31, 232, 0, 0)
4260 case ASUBMECC:
4261 return OPVCC(31, 232, 0, 1)
4262 case ASUBMEV:
4263 return OPVCC(31, 232, 1, 0)
4264 case ASUBMEVCC:
4265 return OPVCC(31, 232, 1, 1)
4266 case ASUBZE:
4267 return OPVCC(31, 200, 0, 0)
4268 case ASUBZECC:
4269 return OPVCC(31, 200, 0, 1)
4270 case ASUBZEV:
4271 return OPVCC(31, 200, 1, 0)
4272 case ASUBZEVCC:
4273 return OPVCC(31, 200, 1, 1)
4274
4275 case ASYNC:
4276 return OPVCC(31, 598, 0, 0)
4277 case ALWSYNC:
4278 return OPVCC(31, 598, 0, 0) | 1<<21
4279
4280 case APTESYNC:
4281 return OPVCC(31, 598, 0, 0) | 2<<21
4282
4283 case ATLBIE:
4284 return OPVCC(31, 306, 0, 0)
4285 case ATLBIEL:
4286 return OPVCC(31, 274, 0, 0)
4287 case ATLBSYNC:
4288 return OPVCC(31, 566, 0, 0)
4289 case ASLBIA:
4290 return OPVCC(31, 498, 0, 0)
4291 case ASLBIE:
4292 return OPVCC(31, 434, 0, 0)
4293 case ASLBMFEE:
4294 return OPVCC(31, 915, 0, 0)
4295 case ASLBMFEV:
4296 return OPVCC(31, 851, 0, 0)
4297 case ASLBMTE:
4298 return OPVCC(31, 402, 0, 0)
4299
4300 case ATW:
4301 return OPVCC(31, 4, 0, 0)
4302 case ATD:
4303 return OPVCC(31, 68, 0, 0)
4304
4305
4306
4307
4308 case AVAND:
4309 return OPVX(4, 1028, 0, 0)
4310 case AVANDC:
4311 return OPVX(4, 1092, 0, 0)
4312 case AVNAND:
4313 return OPVX(4, 1412, 0, 0)
4314
4315 case AVOR:
4316 return OPVX(4, 1156, 0, 0)
4317 case AVORC:
4318 return OPVX(4, 1348, 0, 0)
4319 case AVNOR:
4320 return OPVX(4, 1284, 0, 0)
4321 case AVXOR:
4322 return OPVX(4, 1220, 0, 0)
4323 case AVEQV:
4324 return OPVX(4, 1668, 0, 0)
4325
4326 case AVADDUBM:
4327 return OPVX(4, 0, 0, 0)
4328 case AVADDUHM:
4329 return OPVX(4, 64, 0, 0)
4330 case AVADDUWM:
4331 return OPVX(4, 128, 0, 0)
4332 case AVADDUDM:
4333 return OPVX(4, 192, 0, 0)
4334 case AVADDUQM:
4335 return OPVX(4, 256, 0, 0)
4336
4337 case AVADDCUQ:
4338 return OPVX(4, 320, 0, 0)
4339 case AVADDCUW:
4340 return OPVX(4, 384, 0, 0)
4341
4342 case AVADDUBS:
4343 return OPVX(4, 512, 0, 0)
4344 case AVADDUHS:
4345 return OPVX(4, 576, 0, 0)
4346 case AVADDUWS:
4347 return OPVX(4, 640, 0, 0)
4348
4349 case AVADDSBS:
4350 return OPVX(4, 768, 0, 0)
4351 case AVADDSHS:
4352 return OPVX(4, 832, 0, 0)
4353 case AVADDSWS:
4354 return OPVX(4, 896, 0, 0)
4355
4356 case AVADDEUQM:
4357 return OPVX(4, 60, 0, 0)
4358 case AVADDECUQ:
4359 return OPVX(4, 61, 0, 0)
4360
4361 case AVMULESB:
4362 return OPVX(4, 776, 0, 0)
4363 case AVMULOSB:
4364 return OPVX(4, 264, 0, 0)
4365 case AVMULEUB:
4366 return OPVX(4, 520, 0, 0)
4367 case AVMULOUB:
4368 return OPVX(4, 8, 0, 0)
4369 case AVMULESH:
4370 return OPVX(4, 840, 0, 0)
4371 case AVMULOSH:
4372 return OPVX(4, 328, 0, 0)
4373 case AVMULEUH:
4374 return OPVX(4, 584, 0, 0)
4375 case AVMULOUH:
4376 return OPVX(4, 72, 0, 0)
4377 case AVMULESW:
4378 return OPVX(4, 904, 0, 0)
4379 case AVMULOSW:
4380 return OPVX(4, 392, 0, 0)
4381 case AVMULEUW:
4382 return OPVX(4, 648, 0, 0)
4383 case AVMULOUW:
4384 return OPVX(4, 136, 0, 0)
4385 case AVMULUWM:
4386 return OPVX(4, 137, 0, 0)
4387
4388 case AVPMSUMB:
4389 return OPVX(4, 1032, 0, 0)
4390 case AVPMSUMH:
4391 return OPVX(4, 1096, 0, 0)
4392 case AVPMSUMW:
4393 return OPVX(4, 1160, 0, 0)
4394 case AVPMSUMD:
4395 return OPVX(4, 1224, 0, 0)
4396
4397 case AVMSUMUDM:
4398 return OPVX(4, 35, 0, 0)
4399
4400 case AVSUBUBM:
4401 return OPVX(4, 1024, 0, 0)
4402 case AVSUBUHM:
4403 return OPVX(4, 1088, 0, 0)
4404 case AVSUBUWM:
4405 return OPVX(4, 1152, 0, 0)
4406 case AVSUBUDM:
4407 return OPVX(4, 1216, 0, 0)
4408 case AVSUBUQM:
4409 return OPVX(4, 1280, 0, 0)
4410
4411 case AVSUBCUQ:
4412 return OPVX(4, 1344, 0, 0)
4413 case AVSUBCUW:
4414 return OPVX(4, 1408, 0, 0)
4415
4416 case AVSUBUBS:
4417 return OPVX(4, 1536, 0, 0)
4418 case AVSUBUHS:
4419 return OPVX(4, 1600, 0, 0)
4420 case AVSUBUWS:
4421 return OPVX(4, 1664, 0, 0)
4422
4423 case AVSUBSBS:
4424 return OPVX(4, 1792, 0, 0)
4425 case AVSUBSHS:
4426 return OPVX(4, 1856, 0, 0)
4427 case AVSUBSWS:
4428 return OPVX(4, 1920, 0, 0)
4429
4430 case AVSUBEUQM:
4431 return OPVX(4, 62, 0, 0)
4432 case AVSUBECUQ:
4433 return OPVX(4, 63, 0, 0)
4434
4435 case AVRLB:
4436 return OPVX(4, 4, 0, 0)
4437 case AVRLH:
4438 return OPVX(4, 68, 0, 0)
4439 case AVRLW:
4440 return OPVX(4, 132, 0, 0)
4441 case AVRLD:
4442 return OPVX(4, 196, 0, 0)
4443
4444 case AVMRGOW:
4445 return OPVX(4, 1676, 0, 0)
4446 case AVMRGEW:
4447 return OPVX(4, 1932, 0, 0)
4448
4449 case AVSLB:
4450 return OPVX(4, 260, 0, 0)
4451 case AVSLH:
4452 return OPVX(4, 324, 0, 0)
4453 case AVSLW:
4454 return OPVX(4, 388, 0, 0)
4455 case AVSL:
4456 return OPVX(4, 452, 0, 0)
4457 case AVSLO:
4458 return OPVX(4, 1036, 0, 0)
4459 case AVSRB:
4460 return OPVX(4, 516, 0, 0)
4461 case AVSRH:
4462 return OPVX(4, 580, 0, 0)
4463 case AVSRW:
4464 return OPVX(4, 644, 0, 0)
4465 case AVSR:
4466 return OPVX(4, 708, 0, 0)
4467 case AVSRO:
4468 return OPVX(4, 1100, 0, 0)
4469 case AVSLD:
4470 return OPVX(4, 1476, 0, 0)
4471 case AVSRD:
4472 return OPVX(4, 1732, 0, 0)
4473
4474 case AVSRAB:
4475 return OPVX(4, 772, 0, 0)
4476 case AVSRAH:
4477 return OPVX(4, 836, 0, 0)
4478 case AVSRAW:
4479 return OPVX(4, 900, 0, 0)
4480 case AVSRAD:
4481 return OPVX(4, 964, 0, 0)
4482
4483 case AVBPERMQ:
4484 return OPVC(4, 1356, 0, 0)
4485 case AVBPERMD:
4486 return OPVC(4, 1484, 0, 0)
4487
4488 case AVCLZB:
4489 return OPVX(4, 1794, 0, 0)
4490 case AVCLZH:
4491 return OPVX(4, 1858, 0, 0)
4492 case AVCLZW:
4493 return OPVX(4, 1922, 0, 0)
4494 case AVCLZD:
4495 return OPVX(4, 1986, 0, 0)
4496
4497 case AVPOPCNTB:
4498 return OPVX(4, 1795, 0, 0)
4499 case AVPOPCNTH:
4500 return OPVX(4, 1859, 0, 0)
4501 case AVPOPCNTW:
4502 return OPVX(4, 1923, 0, 0)
4503 case AVPOPCNTD:
4504 return OPVX(4, 1987, 0, 0)
4505
4506 case AVCMPEQUB:
4507 return OPVC(4, 6, 0, 0)
4508 case AVCMPEQUBCC:
4509 return OPVC(4, 6, 0, 1)
4510 case AVCMPEQUH:
4511 return OPVC(4, 70, 0, 0)
4512 case AVCMPEQUHCC:
4513 return OPVC(4, 70, 0, 1)
4514 case AVCMPEQUW:
4515 return OPVC(4, 134, 0, 0)
4516 case AVCMPEQUWCC:
4517 return OPVC(4, 134, 0, 1)
4518 case AVCMPEQUD:
4519 return OPVC(4, 199, 0, 0)
4520 case AVCMPEQUDCC:
4521 return OPVC(4, 199, 0, 1)
4522
4523 case AVCMPGTUB:
4524 return OPVC(4, 518, 0, 0)
4525 case AVCMPGTUBCC:
4526 return OPVC(4, 518, 0, 1)
4527 case AVCMPGTUH:
4528 return OPVC(4, 582, 0, 0)
4529 case AVCMPGTUHCC:
4530 return OPVC(4, 582, 0, 1)
4531 case AVCMPGTUW:
4532 return OPVC(4, 646, 0, 0)
4533 case AVCMPGTUWCC:
4534 return OPVC(4, 646, 0, 1)
4535 case AVCMPGTUD:
4536 return OPVC(4, 711, 0, 0)
4537 case AVCMPGTUDCC:
4538 return OPVC(4, 711, 0, 1)
4539 case AVCMPGTSB:
4540 return OPVC(4, 774, 0, 0)
4541 case AVCMPGTSBCC:
4542 return OPVC(4, 774, 0, 1)
4543 case AVCMPGTSH:
4544 return OPVC(4, 838, 0, 0)
4545 case AVCMPGTSHCC:
4546 return OPVC(4, 838, 0, 1)
4547 case AVCMPGTSW:
4548 return OPVC(4, 902, 0, 0)
4549 case AVCMPGTSWCC:
4550 return OPVC(4, 902, 0, 1)
4551 case AVCMPGTSD:
4552 return OPVC(4, 967, 0, 0)
4553 case AVCMPGTSDCC:
4554 return OPVC(4, 967, 0, 1)
4555
4556 case AVCMPNEZB:
4557 return OPVC(4, 263, 0, 0)
4558 case AVCMPNEZBCC:
4559 return OPVC(4, 263, 0, 1)
4560 case AVCMPNEB:
4561 return OPVC(4, 7, 0, 0)
4562 case AVCMPNEBCC:
4563 return OPVC(4, 7, 0, 1)
4564 case AVCMPNEH:
4565 return OPVC(4, 71, 0, 0)
4566 case AVCMPNEHCC:
4567 return OPVC(4, 71, 0, 1)
4568 case AVCMPNEW:
4569 return OPVC(4, 135, 0, 0)
4570 case AVCMPNEWCC:
4571 return OPVC(4, 135, 0, 1)
4572
4573 case AVPERM:
4574 return OPVX(4, 43, 0, 0)
4575 case AVPERMXOR:
4576 return OPVX(4, 45, 0, 0)
4577 case AVPERMR:
4578 return OPVX(4, 59, 0, 0)
4579
4580 case AVSEL:
4581 return OPVX(4, 42, 0, 0)
4582
4583 case AVCIPHER:
4584 return OPVX(4, 1288, 0, 0)
4585 case AVCIPHERLAST:
4586 return OPVX(4, 1289, 0, 0)
4587 case AVNCIPHER:
4588 return OPVX(4, 1352, 0, 0)
4589 case AVNCIPHERLAST:
4590 return OPVX(4, 1353, 0, 0)
4591 case AVSBOX:
4592 return OPVX(4, 1480, 0, 0)
4593
4594
4595
4596
4597 case AMFVSRD, AMFVRD, AMFFPRD:
4598 return OPVXX1(31, 51, 0)
4599 case AMFVSRWZ:
4600 return OPVXX1(31, 115, 0)
4601 case AMFVSRLD:
4602 return OPVXX1(31, 307, 0)
4603
4604 case AMTVSRD, AMTFPRD, AMTVRD:
4605 return OPVXX1(31, 179, 0)
4606 case AMTVSRWA:
4607 return OPVXX1(31, 211, 0)
4608 case AMTVSRWZ:
4609 return OPVXX1(31, 243, 0)
4610 case AMTVSRDD:
4611 return OPVXX1(31, 435, 0)
4612 case AMTVSRWS:
4613 return OPVXX1(31, 403, 0)
4614
4615 case AXXLAND:
4616 return OPVXX3(60, 130, 0)
4617 case AXXLANDC:
4618 return OPVXX3(60, 138, 0)
4619 case AXXLEQV:
4620 return OPVXX3(60, 186, 0)
4621 case AXXLNAND:
4622 return OPVXX3(60, 178, 0)
4623
4624 case AXXLORC:
4625 return OPVXX3(60, 170, 0)
4626 case AXXLNOR:
4627 return OPVXX3(60, 162, 0)
4628 case AXXLOR, AXXLORQ:
4629 return OPVXX3(60, 146, 0)
4630 case AXXLXOR:
4631 return OPVXX3(60, 154, 0)
4632
4633 case AXXSEL:
4634 return OPVXX4(60, 3, 0)
4635
4636 case AXXMRGHW:
4637 return OPVXX3(60, 18, 0)
4638 case AXXMRGLW:
4639 return OPVXX3(60, 50, 0)
4640
4641 case AXXSPLTW:
4642 return OPVXX2(60, 164, 0)
4643
4644 case AXXSPLTIB:
4645 return OPVCC(60, 360, 0, 0)
4646
4647 case AXXPERM:
4648 return OPVXX3(60, 26, 0)
4649 case AXXPERMDI:
4650 return OPVXX3(60, 10, 0)
4651
4652 case AXXSLDWI:
4653 return OPVXX3(60, 2, 0)
4654
4655 case AXXBRQ:
4656 return OPVXX2VA(60, 475, 31)
4657 case AXXBRD:
4658 return OPVXX2VA(60, 475, 23)
4659 case AXXBRW:
4660 return OPVXX2VA(60, 475, 15)
4661 case AXXBRH:
4662 return OPVXX2VA(60, 475, 7)
4663
4664 case AXSCVDPSP:
4665 return OPVXX2(60, 265, 0)
4666 case AXSCVSPDP:
4667 return OPVXX2(60, 329, 0)
4668 case AXSCVDPSPN:
4669 return OPVXX2(60, 267, 0)
4670 case AXSCVSPDPN:
4671 return OPVXX2(60, 331, 0)
4672
4673 case AXVCVDPSP:
4674 return OPVXX2(60, 393, 0)
4675 case AXVCVSPDP:
4676 return OPVXX2(60, 457, 0)
4677
4678 case AXSCVDPSXDS:
4679 return OPVXX2(60, 344, 0)
4680 case AXSCVDPSXWS:
4681 return OPVXX2(60, 88, 0)
4682 case AXSCVDPUXDS:
4683 return OPVXX2(60, 328, 0)
4684 case AXSCVDPUXWS:
4685 return OPVXX2(60, 72, 0)
4686
4687 case AXSCVSXDDP:
4688 return OPVXX2(60, 376, 0)
4689 case AXSCVUXDDP:
4690 return OPVXX2(60, 360, 0)
4691 case AXSCVSXDSP:
4692 return OPVXX2(60, 312, 0)
4693 case AXSCVUXDSP:
4694 return OPVXX2(60, 296, 0)
4695
4696 case AXVCVDPSXDS:
4697 return OPVXX2(60, 472, 0)
4698 case AXVCVDPSXWS:
4699 return OPVXX2(60, 216, 0)
4700 case AXVCVDPUXDS:
4701 return OPVXX2(60, 456, 0)
4702 case AXVCVDPUXWS:
4703 return OPVXX2(60, 200, 0)
4704 case AXVCVSPSXDS:
4705 return OPVXX2(60, 408, 0)
4706 case AXVCVSPSXWS:
4707 return OPVXX2(60, 152, 0)
4708 case AXVCVSPUXDS:
4709 return OPVXX2(60, 392, 0)
4710 case AXVCVSPUXWS:
4711 return OPVXX2(60, 136, 0)
4712
4713 case AXVCVSXDDP:
4714 return OPVXX2(60, 504, 0)
4715 case AXVCVSXWDP:
4716 return OPVXX2(60, 248, 0)
4717 case AXVCVUXDDP:
4718 return OPVXX2(60, 488, 0)
4719 case AXVCVUXWDP:
4720 return OPVXX2(60, 232, 0)
4721 case AXVCVSXDSP:
4722 return OPVXX2(60, 440, 0)
4723 case AXVCVSXWSP:
4724 return OPVXX2(60, 184, 0)
4725 case AXVCVUXDSP:
4726 return OPVXX2(60, 424, 0)
4727 case AXVCVUXWSP:
4728 return OPVXX2(60, 168, 0)
4729
4730
4731 case AMADDHD:
4732 return OPVX(4, 48, 0, 0)
4733 case AMADDHDU:
4734 return OPVX(4, 49, 0, 0)
4735 case AMADDLD:
4736 return OPVX(4, 51, 0, 0)
4737
4738 case AXOR:
4739 return OPVCC(31, 316, 0, 0)
4740 case AXORCC:
4741 return OPVCC(31, 316, 0, 1)
4742 }
4743
4744 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
4745 return 0
4746 }
4747
4748 func (c *ctxt9) opirrr(a obj.As) uint32 {
4749 switch a {
4750
4751
4752
4753 case AVSLDOI:
4754 return OPVX(4, 44, 0, 0)
4755 }
4756
4757 c.ctxt.Diag("bad i/r/r/r opcode %v", a)
4758 return 0
4759 }
4760
4761 func (c *ctxt9) opiirr(a obj.As) uint32 {
4762 switch a {
4763
4764
4765 case AVSHASIGMAW:
4766 return OPVX(4, 1666, 0, 0)
4767 case AVSHASIGMAD:
4768 return OPVX(4, 1730, 0, 0)
4769 }
4770
4771 c.ctxt.Diag("bad i/i/r/r opcode %v", a)
4772 return 0
4773 }
4774
4775 func (c *ctxt9) opirr(a obj.As) uint32 {
4776 switch a {
4777 case AADD:
4778 return OPVCC(14, 0, 0, 0)
4779 case AADDC:
4780 return OPVCC(12, 0, 0, 0)
4781 case AADDCCC:
4782 return OPVCC(13, 0, 0, 0)
4783 case AADDIS:
4784 return OPVCC(15, 0, 0, 0)
4785
4786 case AANDCC:
4787 return OPVCC(28, 0, 0, 0)
4788 case AANDISCC:
4789 return OPVCC(29, 0, 0, 0)
4790
4791 case ABR:
4792 return OPVCC(18, 0, 0, 0)
4793 case ABL:
4794 return OPVCC(18, 0, 0, 0) | 1
4795 case obj.ADUFFZERO:
4796 return OPVCC(18, 0, 0, 0) | 1
4797 case obj.ADUFFCOPY:
4798 return OPVCC(18, 0, 0, 0) | 1
4799 case ABC:
4800 return OPVCC(16, 0, 0, 0)
4801 case ABCL:
4802 return OPVCC(16, 0, 0, 0) | 1
4803
4804 case ABEQ:
4805 return AOP_RRR(16<<26, 12, 2, 0)
4806 case ABGE:
4807 return AOP_RRR(16<<26, 4, 0, 0)
4808 case ABGT:
4809 return AOP_RRR(16<<26, 12, 1, 0)
4810 case ABLE:
4811 return AOP_RRR(16<<26, 4, 1, 0)
4812 case ABLT:
4813 return AOP_RRR(16<<26, 12, 0, 0)
4814 case ABNE:
4815 return AOP_RRR(16<<26, 4, 2, 0)
4816 case ABVC:
4817 return AOP_RRR(16<<26, 4, 3, 0)
4818 case ABVS:
4819 return AOP_RRR(16<<26, 12, 3, 0)
4820
4821 case ACMP:
4822 return OPVCC(11, 0, 0, 0) | 1<<21
4823 case ACMPU:
4824 return OPVCC(10, 0, 0, 0) | 1<<21
4825 case ACMPW:
4826 return OPVCC(11, 0, 0, 0)
4827 case ACMPWU:
4828 return OPVCC(10, 0, 0, 0)
4829 case ACMPEQB:
4830 return OPVCC(31, 224, 0, 0)
4831
4832 case ALSW:
4833 return OPVCC(31, 597, 0, 0)
4834
4835 case ACOPY:
4836 return OPVCC(31, 774, 0, 0)
4837 case APASTECC:
4838 return OPVCC(31, 902, 0, 1)
4839 case ADARN:
4840 return OPVCC(31, 755, 0, 0)
4841
4842 case AMULLW, AMULLD:
4843 return OPVCC(7, 0, 0, 0)
4844
4845 case AOR:
4846 return OPVCC(24, 0, 0, 0)
4847 case AORIS:
4848 return OPVCC(25, 0, 0, 0)
4849
4850 case ARLWMI:
4851 return OPVCC(20, 0, 0, 0)
4852 case ARLWMICC:
4853 return OPVCC(20, 0, 0, 1)
4854 case ARLDMI:
4855 return OPMD(30, 3, 0)
4856 case ARLDMICC:
4857 return OPMD(30, 3, 1)
4858 case ARLDIMI:
4859 return OPMD(30, 3, 0)
4860 case ARLDIMICC:
4861 return OPMD(30, 3, 1)
4862 case ARLWNM:
4863 return OPVCC(21, 0, 0, 0)
4864 case ARLWNMCC:
4865 return OPVCC(21, 0, 0, 1)
4866
4867 case ARLDCL:
4868 return OPMD(30, 0, 0)
4869 case ARLDCLCC:
4870 return OPMD(30, 0, 1)
4871 case ARLDCR:
4872 return OPMD(30, 1, 0)
4873 case ARLDCRCC:
4874 return OPMD(30, 1, 1)
4875 case ARLDC:
4876 return OPMD(30, 2, 0)
4877 case ARLDCCC:
4878 return OPMD(30, 2, 1)
4879
4880 case ASRAW:
4881 return OPVCC(31, 824, 0, 0)
4882 case ASRAWCC:
4883 return OPVCC(31, 824, 0, 1)
4884 case ASRAD:
4885 return OPVCC(31, (413 << 1), 0, 0)
4886 case ASRADCC:
4887 return OPVCC(31, (413 << 1), 0, 1)
4888 case AEXTSWSLI:
4889 return OPVCC(31, 445, 0, 0)
4890 case AEXTSWSLICC:
4891 return OPVCC(31, 445, 0, 1)
4892
4893 case ASTSW:
4894 return OPVCC(31, 725, 0, 0)
4895
4896 case ASUBC:
4897 return OPVCC(8, 0, 0, 0)
4898
4899 case ATW:
4900 return OPVCC(3, 0, 0, 0)
4901 case ATD:
4902 return OPVCC(2, 0, 0, 0)
4903
4904
4905
4906
4907 case AVSPLTB:
4908 return OPVX(4, 524, 0, 0)
4909 case AVSPLTH:
4910 return OPVX(4, 588, 0, 0)
4911 case AVSPLTW:
4912 return OPVX(4, 652, 0, 0)
4913
4914 case AVSPLTISB:
4915 return OPVX(4, 780, 0, 0)
4916 case AVSPLTISH:
4917 return OPVX(4, 844, 0, 0)
4918 case AVSPLTISW:
4919 return OPVX(4, 908, 0, 0)
4920
4921
4922 case AFTDIV:
4923 return OPVCC(63, 128, 0, 0)
4924 case AFTSQRT:
4925 return OPVCC(63, 160, 0, 0)
4926
4927 case AXOR:
4928 return OPVCC(26, 0, 0, 0)
4929 case AXORIS:
4930 return OPVCC(27, 0, 0, 0)
4931 }
4932
4933 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
4934 return 0
4935 }
4936
4937
4940 func (c *ctxt9) opload(a obj.As) uint32 {
4941 switch a {
4942 case AMOVD:
4943 return OPVCC(58, 0, 0, 0)
4944 case AMOVDU:
4945 return OPVCC(58, 0, 0, 1)
4946 case AMOVWZ:
4947 return OPVCC(32, 0, 0, 0)
4948 case AMOVWZU:
4949 return OPVCC(33, 0, 0, 0)
4950 case AMOVW:
4951 return OPVCC(58, 0, 0, 0) | 1<<1
4952 case ALXV:
4953 return OPDQ(61, 1, 0)
4954 case ALXVL:
4955 return OPVXX1(31, 269, 0)
4956 case ALXVLL:
4957 return OPVXX1(31, 301, 0)
4958 case ALXVX:
4959 return OPVXX1(31, 268, 0)
4960
4961
4962 case AMOVB, AMOVBZ:
4963 return OPVCC(34, 0, 0, 0)
4964
4965
4966 case AMOVBU, AMOVBZU:
4967 return OPVCC(35, 0, 0, 0)
4968 case AFMOVD:
4969 return OPVCC(50, 0, 0, 0)
4970 case AFMOVDU:
4971 return OPVCC(51, 0, 0, 0)
4972 case AFMOVS:
4973 return OPVCC(48, 0, 0, 0)
4974 case AFMOVSU:
4975 return OPVCC(49, 0, 0, 0)
4976 case AMOVH:
4977 return OPVCC(42, 0, 0, 0)
4978 case AMOVHU:
4979 return OPVCC(43, 0, 0, 0)
4980 case AMOVHZ:
4981 return OPVCC(40, 0, 0, 0)
4982 case AMOVHZU:
4983 return OPVCC(41, 0, 0, 0)
4984 case AMOVMW:
4985 return OPVCC(46, 0, 0, 0)
4986 }
4987
4988 c.ctxt.Diag("bad load opcode %v", a)
4989 return 0
4990 }
4991
4992
4995 func (c *ctxt9) oploadx(a obj.As) uint32 {
4996 switch a {
4997 case AMOVWZ:
4998 return OPVCC(31, 23, 0, 0)
4999 case AMOVWZU:
5000 return OPVCC(31, 55, 0, 0)
5001 case AMOVW:
5002 return OPVCC(31, 341, 0, 0)
5003 case AMOVWU:
5004 return OPVCC(31, 373, 0, 0)
5005
5006 case AMOVB, AMOVBZ:
5007 return OPVCC(31, 87, 0, 0)
5008
5009 case AMOVBU, AMOVBZU:
5010 return OPVCC(31, 119, 0, 0)
5011 case AFMOVD:
5012 return OPVCC(31, 599, 0, 0)
5013 case AFMOVDU:
5014 return OPVCC(31, 631, 0, 0)
5015 case AFMOVS:
5016 return OPVCC(31, 535, 0, 0)
5017 case AFMOVSU:
5018 return OPVCC(31, 567, 0, 0)
5019 case AFMOVSX:
5020 return OPVCC(31, 855, 0, 0)
5021 case AFMOVSZ:
5022 return OPVCC(31, 887, 0, 0)
5023 case AMOVH:
5024 return OPVCC(31, 343, 0, 0)
5025 case AMOVHU:
5026 return OPVCC(31, 375, 0, 0)
5027 case AMOVHBR:
5028 return OPVCC(31, 790, 0, 0)
5029 case AMOVWBR:
5030 return OPVCC(31, 534, 0, 0)
5031 case AMOVDBR:
5032 return OPVCC(31, 532, 0, 0)
5033 case AMOVHZ:
5034 return OPVCC(31, 279, 0, 0)
5035 case AMOVHZU:
5036 return OPVCC(31, 311, 0, 0)
5037 case AECIWX:
5038 return OPVCC(31, 310, 0, 0)
5039 case ALBAR:
5040 return OPVCC(31, 52, 0, 0)
5041 case ALHAR:
5042 return OPVCC(31, 116, 0, 0)
5043 case ALWAR:
5044 return OPVCC(31, 20, 0, 0)
5045 case ALDAR:
5046 return OPVCC(31, 84, 0, 0)
5047 case ALSW:
5048 return OPVCC(31, 533, 0, 0)
5049 case AMOVD:
5050 return OPVCC(31, 21, 0, 0)
5051 case AMOVDU:
5052 return OPVCC(31, 53, 0, 0)
5053 case ALDMX:
5054 return OPVCC(31, 309, 0, 0)
5055
5056
5057 case ALVEBX:
5058 return OPVCC(31, 7, 0, 0)
5059 case ALVEHX:
5060 return OPVCC(31, 39, 0, 0)
5061 case ALVEWX:
5062 return OPVCC(31, 71, 0, 0)
5063 case ALVX:
5064 return OPVCC(31, 103, 0, 0)
5065 case ALVXL:
5066 return OPVCC(31, 359, 0, 0)
5067 case ALVSL:
5068 return OPVCC(31, 6, 0, 0)
5069 case ALVSR:
5070 return OPVCC(31, 38, 0, 0)
5071
5072
5073
5074 case ALXVX:
5075 return OPVXX1(31, 268, 0)
5076 case ALXVD2X:
5077 return OPVXX1(31, 844, 0)
5078 case ALXVW4X:
5079 return OPVXX1(31, 780, 0)
5080 case ALXVH8X:
5081 return OPVXX1(31, 812, 0)
5082 case ALXVB16X:
5083 return OPVXX1(31, 876, 0)
5084 case ALXVDSX:
5085 return OPVXX1(31, 332, 0)
5086 case ALXSDX:
5087 return OPVXX1(31, 588, 0)
5088 case ALXSIWAX:
5089 return OPVXX1(31, 76, 0)
5090 case ALXSIWZX:
5091 return OPVXX1(31, 12, 0)
5092 }
5093
5094 c.ctxt.Diag("bad loadx opcode %v", a)
5095 return 0
5096 }
5097
5098
5101 func (c *ctxt9) opstore(a obj.As) uint32 {
5102 switch a {
5103 case AMOVB, AMOVBZ:
5104 return OPVCC(38, 0, 0, 0)
5105
5106 case AMOVBU, AMOVBZU:
5107 return OPVCC(39, 0, 0, 0)
5108 case AFMOVD:
5109 return OPVCC(54, 0, 0, 0)
5110 case AFMOVDU:
5111 return OPVCC(55, 0, 0, 0)
5112 case AFMOVS:
5113 return OPVCC(52, 0, 0, 0)
5114 case AFMOVSU:
5115 return OPVCC(53, 0, 0, 0)
5116
5117 case AMOVHZ, AMOVH:
5118 return OPVCC(44, 0, 0, 0)
5119
5120 case AMOVHZU, AMOVHU:
5121 return OPVCC(45, 0, 0, 0)
5122 case AMOVMW:
5123 return OPVCC(47, 0, 0, 0)
5124 case ASTSW:
5125 return OPVCC(31, 725, 0, 0)
5126
5127 case AMOVWZ, AMOVW:
5128 return OPVCC(36, 0, 0, 0)
5129
5130 case AMOVWZU, AMOVWU:
5131 return OPVCC(37, 0, 0, 0)
5132 case AMOVD:
5133 return OPVCC(62, 0, 0, 0)
5134 case AMOVDU:
5135 return OPVCC(62, 0, 0, 1)
5136 case ASTXV:
5137 return OPDQ(61, 5, 0)
5138 case ASTXVL:
5139 return OPVXX1(31, 397, 0)
5140 case ASTXVLL:
5141 return OPVXX1(31, 429, 0)
5142 case ASTXVX:
5143 return OPVXX1(31, 396, 0)
5144
5145 }
5146
5147 c.ctxt.Diag("unknown store opcode %v", a)
5148 return 0
5149 }
5150
5151
5154 func (c *ctxt9) opstorex(a obj.As) uint32 {
5155 switch a {
5156 case AMOVB, AMOVBZ:
5157 return OPVCC(31, 215, 0, 0)
5158
5159 case AMOVBU, AMOVBZU:
5160 return OPVCC(31, 247, 0, 0)
5161 case AFMOVD:
5162 return OPVCC(31, 727, 0, 0)
5163 case AFMOVDU:
5164 return OPVCC(31, 759, 0, 0)
5165 case AFMOVS:
5166 return OPVCC(31, 663, 0, 0)
5167 case AFMOVSU:
5168 return OPVCC(31, 695, 0, 0)
5169 case AFMOVSX:
5170 return OPVCC(31, 983, 0, 0)
5171
5172 case AMOVHZ, AMOVH:
5173 return OPVCC(31, 407, 0, 0)
5174 case AMOVHBR:
5175 return OPVCC(31, 918, 0, 0)
5176
5177 case AMOVHZU, AMOVHU:
5178 return OPVCC(31, 439, 0, 0)
5179
5180 case AMOVWZ, AMOVW:
5181 return OPVCC(31, 151, 0, 0)
5182
5183 case AMOVWZU, AMOVWU:
5184 return OPVCC(31, 183, 0, 0)
5185 case ASTSW:
5186 return OPVCC(31, 661, 0, 0)
5187 case AMOVWBR:
5188 return OPVCC(31, 662, 0, 0)
5189 case AMOVDBR:
5190 return OPVCC(31, 660, 0, 0)
5191 case ASTBCCC:
5192 return OPVCC(31, 694, 0, 1)
5193 case ASTHCCC:
5194 return OPVCC(31, 726, 0, 1)
5195 case ASTWCCC:
5196 return OPVCC(31, 150, 0, 1)
5197 case ASTDCCC:
5198 return OPVCC(31, 214, 0, 1)
5199 case AECOWX:
5200 return OPVCC(31, 438, 0, 0)
5201 case AMOVD:
5202 return OPVCC(31, 149, 0, 0)
5203 case AMOVDU:
5204 return OPVCC(31, 181, 0, 0)
5205
5206
5207 case ASTVEBX:
5208 return OPVCC(31, 135, 0, 0)
5209 case ASTVEHX:
5210 return OPVCC(31, 167, 0, 0)
5211 case ASTVEWX:
5212 return OPVCC(31, 199, 0, 0)
5213 case ASTVX:
5214 return OPVCC(31, 231, 0, 0)
5215 case ASTVXL:
5216 return OPVCC(31, 487, 0, 0)
5217
5218
5219
5220 case ASTXVX:
5221 return OPVXX1(31, 396, 0)
5222 case ASTXVD2X:
5223 return OPVXX1(31, 972, 0)
5224 case ASTXVW4X:
5225 return OPVXX1(31, 908, 0)
5226 case ASTXVH8X:
5227 return OPVXX1(31, 940, 0)
5228 case ASTXVB16X:
5229 return OPVXX1(31, 1004, 0)
5230
5231 case ASTXSDX:
5232 return OPVXX1(31, 716, 0)
5233
5234 case ASTXSIWX:
5235 return OPVXX1(31, 140, 0)
5236
5237
5238
5239 }
5240
5241 c.ctxt.Diag("unknown storex opcode %v", a)
5242 return 0
5243 }
5244
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