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30 package s390x
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "fmt"
36 "log"
37 "math"
38 "sort"
39 )
40
41
42
43
44 type ctxtz struct {
45 ctxt *obj.Link
46 newprog obj.ProgAlloc
47 cursym *obj.LSym
48 autosize int32
49 instoffset int64
50 pc int64
51 }
52
53
54 const (
55 funcAlign = 16
56 )
57
58 type Optab struct {
59 as obj.As
60 i uint8
61 a1 uint8
62 a2 uint8
63 a3 uint8
64 a4 uint8
65 a5 uint8
66 a6 uint8
67 }
68
69 var optab = []Optab{
70
71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
75 {i: 0, as: obj.ANOP},
76 {i: 0, as: obj.ANOP, a1: C_SAUTO},
77
78
79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
86
87
88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
96
97
98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
118
119
120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
139
140
141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
160
161
162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
163
164
165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
166 {i: 2, as: AADD, a1: C_REG, a6: C_REG},
167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG},
169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG},
178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG},
182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG},
183 {i: 47, as: ANEG, a6: C_REG},
184
185
186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
187 {i: 6, as: AAND, a1: C_REG, a6: C_REG},
188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG},
189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG},
193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG},
197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
201
202
203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
204
205
206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
208 {i: 33, as: AFABS, a6: C_FREG},
209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
226
227
228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
232
233
234 {i: 5, as: ASYSCALL},
235 {i: 77, as: ASYSCALL, a1: C_SCON},
236
237
238 {i: 16, as: ABEQ, a6: C_SBRA},
239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA},
240 {i: 11, as: ABR, a6: C_LBRA},
241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
242 {i: 18, as: ABR, a6: C_REG},
243 {i: 18, as: ABR, a1: C_REG, a6: C_REG},
244 {i: 15, as: ABR, a6: C_ZOREG},
245 {i: 15, as: ABC, a6: C_ZOREG},
246
247
248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA},
254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
258
259
260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA},
261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA},
262
263
264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
265
266
267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},
268
269
270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
271
272
273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
274
275
276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG},
277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
282
283
284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
285
286
287 {i: 92, as: AIPM, a1: C_REG},
288
289
290 {i: 76, as: ASPM, a1: C_REG},
291
292
293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
297
298
299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
301
302
303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
307
308
309 {i: 40, as: ABYTE, a1: C_SCON},
310 {i: 40, as: AWORD, a1: C_LCON},
311 {i: 31, as: ADWORD, a1: C_LCON},
312 {i: 31, as: ADWORD, a1: C_DCON},
313
314
315 {i: 80, as: ASYNC},
316
317
318 {i: 88, as: ASTCK, a6: C_SAUTO},
319 {i: 88, as: ASTCK, a6: C_SOREG},
320
321
322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
325
326
327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
332
333
334 {i: 78, as: obj.AUNDEF},
335
336
337 {i: 66, as: ANOPH},
338
339
340
341
342 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
343 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
344 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
345 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
346
347
348 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
349 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
350 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
351 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
352
353
354 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
355 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
356
357
358 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
359 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
360
361
362 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
363 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
364 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
365 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
366 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
367 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
368 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
369 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
370
371
372 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
373 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
374
375
376 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
377 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
378
379
380 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
381 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
382
383
384 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
385 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
386
387
388 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
389 {i: 109, as: AVZERO, a6: C_VREG},
390 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
391 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
392 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
393 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
394
395
396 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
397
398
399 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
400
401
402
403 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
404 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
405
406
407 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
408
409
410 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
411
412
413 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
414
415
416 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
417 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
418 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
419
420
421 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
422 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
423 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
424 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
425
426
427 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
428 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
429
430
431 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
432
433
434 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
435
436
437 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
438 }
439
440 var oprange [ALAST & obj.AMask][]Optab
441
442 var xcmp [C_NCLASS][C_NCLASS]bool
443
444 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
445 if ctxt.Retpoline {
446 ctxt.Diag("-spectre=ret not supported on s390x")
447 ctxt.Retpoline = false
448 }
449
450 p := cursym.Func().Text
451 if p == nil || p.Link == nil {
452 return
453 }
454
455 if oprange[AORW&obj.AMask] == nil {
456 ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
457 }
458
459 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
460
461 buffer := make([]byte, 0)
462 changed := true
463 loop := 0
464 nrelocs0 := len(c.cursym.R)
465 for changed {
466 if loop > 100 {
467 c.ctxt.Diag("stuck in spanz loop")
468 break
469 }
470 changed = false
471 buffer = buffer[:0]
472 for i := range c.cursym.R[nrelocs0:] {
473 c.cursym.R[nrelocs0+i] = obj.Reloc{}
474 }
475 c.cursym.R = c.cursym.R[:nrelocs0]
476 for p := c.cursym.Func().Text; p != nil; p = p.Link {
477 pc := int64(len(buffer))
478 if pc != p.Pc {
479 changed = true
480 }
481 p.Pc = pc
482 c.pc = p.Pc
483 c.asmout(p, &buffer)
484 if pc == int64(len(buffer)) {
485 switch p.As {
486 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
487
488 default:
489 c.ctxt.Diag("zero-width instruction\n%v", p)
490 }
491 }
492 }
493 loop++
494 }
495
496 c.cursym.Size = int64(len(buffer))
497 if c.cursym.Size%funcAlign != 0 {
498 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
499 }
500 c.cursym.Grow(c.cursym.Size)
501 copy(c.cursym.P, buffer)
502
503
504
505
506
507 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil)
508 }
509
510
511 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool {
512 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP {
513 return true
514 }
515 for _, a := range p.RestArgs {
516 if a.Reg == REGTMP {
517 return true
518 }
519 }
520 return p.Mark&USETMP != 0
521 }
522
523 func isint32(v int64) bool {
524 return int64(int32(v)) == v
525 }
526
527 func isuint32(v uint64) bool {
528 return uint64(uint32(v)) == v
529 }
530
531 func (c *ctxtz) aclass(a *obj.Addr) int {
532 switch a.Type {
533 case obj.TYPE_NONE:
534 return C_NONE
535
536 case obj.TYPE_REG:
537 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
538 return C_REG
539 }
540 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
541 return C_FREG
542 }
543 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
544 return C_AREG
545 }
546 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
547 return C_VREG
548 }
549 return C_GOK
550
551 case obj.TYPE_MEM:
552 switch a.Name {
553 case obj.NAME_EXTERN,
554 obj.NAME_STATIC:
555 if a.Sym == nil {
556
557 break
558 }
559 c.instoffset = a.Offset
560 if a.Sym.Type == objabi.STLSBSS {
561 if c.ctxt.Flag_shared {
562 return C_TLS_IE
563 }
564 return C_TLS_LE
565 }
566 return C_ADDR
567
568 case obj.NAME_GOTREF:
569 return C_GOTADDR
570
571 case obj.NAME_AUTO:
572 if a.Reg == REGSP {
573
574
575 a.Reg = obj.REG_NONE
576 }
577 c.instoffset = int64(c.autosize) + a.Offset
578 if c.instoffset >= -BIG && c.instoffset < BIG {
579 return C_SAUTO
580 }
581 return C_LAUTO
582
583 case obj.NAME_PARAM:
584 if a.Reg == REGSP {
585
586
587 a.Reg = obj.REG_NONE
588 }
589 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
590 if c.instoffset >= -BIG && c.instoffset < BIG {
591 return C_SAUTO
592 }
593 return C_LAUTO
594
595 case obj.NAME_NONE:
596 c.instoffset = a.Offset
597 if c.instoffset == 0 {
598 return C_ZOREG
599 }
600 if c.instoffset >= -BIG && c.instoffset < BIG {
601 return C_SOREG
602 }
603 return C_LOREG
604 }
605
606 return C_GOK
607
608 case obj.TYPE_TEXTSIZE:
609 return C_TEXTSIZE
610
611 case obj.TYPE_FCONST:
612 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
613 return C_ZCON
614 }
615 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
616
617 case obj.TYPE_CONST,
618 obj.TYPE_ADDR:
619 switch a.Name {
620 case obj.NAME_NONE:
621 c.instoffset = a.Offset
622 if a.Reg != 0 {
623 if -BIG <= c.instoffset && c.instoffset <= BIG {
624 return C_SACON
625 }
626 if isint32(c.instoffset) {
627 return C_LACON
628 }
629 return C_DACON
630 }
631
632 case obj.NAME_EXTERN,
633 obj.NAME_STATIC:
634 s := a.Sym
635 if s == nil {
636 return C_GOK
637 }
638 c.instoffset = a.Offset
639
640 return C_SYMADDR
641
642 case obj.NAME_AUTO:
643 if a.Reg == REGSP {
644
645
646 a.Reg = obj.REG_NONE
647 }
648 c.instoffset = int64(c.autosize) + a.Offset
649 if c.instoffset >= -BIG && c.instoffset < BIG {
650 return C_SACON
651 }
652 return C_LACON
653
654 case obj.NAME_PARAM:
655 if a.Reg == REGSP {
656
657
658 a.Reg = obj.REG_NONE
659 }
660 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
661 if c.instoffset >= -BIG && c.instoffset < BIG {
662 return C_SACON
663 }
664 return C_LACON
665
666 default:
667 return C_GOK
668 }
669
670 if c.instoffset == 0 {
671 return C_ZCON
672 }
673 if c.instoffset >= 0 {
674 if c.instoffset <= 0x7fff {
675 return C_SCON
676 }
677 if c.instoffset <= 0xffff {
678 return C_ANDCON
679 }
680 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
681 return C_UCON
682 }
683 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
684 return C_LCON
685 }
686 return C_DCON
687 }
688
689 if c.instoffset >= -0x8000 {
690 return C_ADDCON
691 }
692 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
693 return C_UCON
694 }
695 if isint32(c.instoffset) {
696 return C_LCON
697 }
698 return C_DCON
699
700 case obj.TYPE_BRANCH:
701 return C_SBRA
702 }
703
704 return C_GOK
705 }
706
707 func (c *ctxtz) oplook(p *obj.Prog) *Optab {
708
709 if p.Optab != 0 {
710 return &optab[p.Optab-1]
711 }
712 if len(p.RestArgs) > 3 {
713 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
714 return nil
715 }
716
717
718 p.From.Class = int8(c.aclass(&p.From) + 1)
719 p.To.Class = int8(c.aclass(&p.To) + 1)
720 for i := range p.RestArgs {
721 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1)
722 }
723
724
725 args := [...]int8{
726 p.From.Class - 1,
727 C_NONE,
728 C_NONE,
729 C_NONE,
730 C_NONE,
731 p.To.Class - 1,
732 }
733
734 switch {
735 case REG_R0 <= p.Reg && p.Reg <= REG_R15:
736 args[1] = C_REG
737 case REG_V0 <= p.Reg && p.Reg <= REG_V31:
738 args[1] = C_VREG
739 case REG_F0 <= p.Reg && p.Reg <= REG_F15:
740 args[1] = C_FREG
741 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
742 args[1] = C_AREG
743 }
744
745 for i, a := range p.RestArgs {
746 args[2+i] = a.Class - 1
747 }
748
749
750 ops := oprange[p.As&obj.AMask]
751 cmp := [len(args)]*[C_NCLASS]bool{}
752 for i := range cmp {
753 cmp[i] = &xcmp[args[i]]
754 }
755 for i := range ops {
756 op := &ops[i]
757 if cmp[0][op.a1] && cmp[1][op.a2] &&
758 cmp[2][op.a3] && cmp[3][op.a4] &&
759 cmp[4][op.a5] && cmp[5][op.a6] {
760 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
761 return op
762 }
763 }
764
765
766 s := ""
767 for _, a := range args {
768 s += fmt.Sprintf(" %v", DRconv(int(a)))
769 }
770 c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
771 c.ctxt.Diag("prog: %v\n", p)
772 return nil
773 }
774
775 func cmp(a int, b int) bool {
776 if a == b {
777 return true
778 }
779 switch a {
780 case C_DCON:
781 if b == C_LCON {
782 return true
783 }
784 fallthrough
785 case C_LCON:
786 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
787 return true
788 }
789
790 case C_ADDCON:
791 if b == C_ZCON || b == C_SCON {
792 return true
793 }
794
795 case C_ANDCON:
796 if b == C_ZCON || b == C_SCON {
797 return true
798 }
799
800 case C_UCON:
801 if b == C_ZCON || b == C_SCON {
802 return true
803 }
804
805 case C_SCON:
806 if b == C_ZCON {
807 return true
808 }
809
810 case C_LACON:
811 if b == C_SACON {
812 return true
813 }
814
815 case C_LBRA:
816 if b == C_SBRA {
817 return true
818 }
819
820 case C_LAUTO:
821 if b == C_SAUTO {
822 return true
823 }
824
825 case C_LOREG:
826 if b == C_ZOREG || b == C_SOREG {
827 return true
828 }
829
830 case C_SOREG:
831 if b == C_ZOREG {
832 return true
833 }
834
835 case C_ANY:
836 return true
837 }
838
839 return false
840 }
841
842 type ocmp []Optab
843
844 func (x ocmp) Len() int {
845 return len(x)
846 }
847
848 func (x ocmp) Swap(i, j int) {
849 x[i], x[j] = x[j], x[i]
850 }
851
852 func (x ocmp) Less(i, j int) bool {
853 p1 := &x[i]
854 p2 := &x[j]
855 n := int(p1.as) - int(p2.as)
856 if n != 0 {
857 return n < 0
858 }
859 n = int(p1.a1) - int(p2.a1)
860 if n != 0 {
861 return n < 0
862 }
863 n = int(p1.a2) - int(p2.a2)
864 if n != 0 {
865 return n < 0
866 }
867 n = int(p1.a3) - int(p2.a3)
868 if n != 0 {
869 return n < 0
870 }
871 n = int(p1.a4) - int(p2.a4)
872 if n != 0 {
873 return n < 0
874 }
875 return false
876 }
877 func opset(a, b obj.As) {
878 oprange[a&obj.AMask] = oprange[b&obj.AMask]
879 }
880
881 func buildop(ctxt *obj.Link) {
882 if oprange[AORW&obj.AMask] != nil {
883
884
885
886 return
887 }
888
889 for i := 0; i < C_NCLASS; i++ {
890 for n := 0; n < C_NCLASS; n++ {
891 if cmp(n, i) {
892 xcmp[i][n] = true
893 }
894 }
895 }
896 sort.Sort(ocmp(optab))
897 for i := 0; i < len(optab); i++ {
898 r := optab[i].as
899 start := i
900 for ; i+1 < len(optab); i++ {
901 if optab[i+1].as != r {
902 break
903 }
904 }
905 oprange[r&obj.AMask] = optab[start : i+1]
906
907
908
909 switch r {
910 case AADD:
911 opset(AADDC, r)
912 opset(AADDW, r)
913 opset(AADDE, r)
914 opset(AMULLD, r)
915 opset(AMULLW, r)
916 case ADIVW:
917 opset(ADIVD, r)
918 opset(ADIVDU, r)
919 opset(ADIVWU, r)
920 opset(AMODD, r)
921 opset(AMODDU, r)
922 opset(AMODW, r)
923 opset(AMODWU, r)
924 case AMULHD:
925 opset(AMULHDU, r)
926 case AMOVBZ:
927 opset(AMOVH, r)
928 opset(AMOVHZ, r)
929 case ALA:
930 opset(ALAY, r)
931 case AMVC:
932 opset(AMVCIN, r)
933 opset(ACLC, r)
934 opset(AXC, r)
935 opset(AOC, r)
936 opset(ANC, r)
937 case ASTCK:
938 opset(ASTCKC, r)
939 opset(ASTCKE, r)
940 opset(ASTCKF, r)
941 case ALAAG:
942 opset(ALAA, r)
943 opset(ALAAL, r)
944 opset(ALAALG, r)
945 opset(ALAN, r)
946 opset(ALANG, r)
947 opset(ALAX, r)
948 opset(ALAXG, r)
949 opset(ALAO, r)
950 opset(ALAOG, r)
951 case ASTMG:
952 opset(ASTMY, r)
953 case ALMG:
954 opset(ALMY, r)
955 case ABEQ:
956 opset(ABGE, r)
957 opset(ABGT, r)
958 opset(ABLE, r)
959 opset(ABLT, r)
960 opset(ABNE, r)
961 opset(ABVC, r)
962 opset(ABVS, r)
963 opset(ABLEU, r)
964 opset(ABLTU, r)
965 case ABR:
966 opset(ABL, r)
967 case ABC:
968 opset(ABCL, r)
969 case AFABS:
970 opset(AFNABS, r)
971 opset(ALPDFR, r)
972 opset(ALNDFR, r)
973 opset(AFNEG, r)
974 opset(AFNEGS, r)
975 opset(ALEDBR, r)
976 opset(ALDEBR, r)
977 opset(AFSQRT, r)
978 opset(AFSQRTS, r)
979 case AFADD:
980 opset(AFADDS, r)
981 opset(AFDIV, r)
982 opset(AFDIVS, r)
983 opset(AFSUB, r)
984 opset(AFSUBS, r)
985 case AFMADD:
986 opset(AFMADDS, r)
987 opset(AFMSUB, r)
988 opset(AFMSUBS, r)
989 case AFMUL:
990 opset(AFMULS, r)
991 case AFCMPO:
992 opset(AFCMPU, r)
993 opset(ACEBR, r)
994 case AAND:
995 opset(AOR, r)
996 opset(AXOR, r)
997 case AANDW:
998 opset(AORW, r)
999 opset(AXORW, r)
1000 case ASLD:
1001 opset(ASRD, r)
1002 opset(ASLW, r)
1003 opset(ASRW, r)
1004 opset(ASRAD, r)
1005 opset(ASRAW, r)
1006 opset(ARLL, r)
1007 opset(ARLLG, r)
1008 case ARNSBG:
1009 opset(ARXSBG, r)
1010 opset(AROSBG, r)
1011 opset(ARNSBGT, r)
1012 opset(ARXSBGT, r)
1013 opset(AROSBGT, r)
1014 opset(ARISBG, r)
1015 opset(ARISBGN, r)
1016 opset(ARISBGZ, r)
1017 opset(ARISBGNZ, r)
1018 opset(ARISBHG, r)
1019 opset(ARISBLG, r)
1020 opset(ARISBHGZ, r)
1021 opset(ARISBLGZ, r)
1022 case ACSG:
1023 opset(ACS, r)
1024 case ASUB:
1025 opset(ASUBC, r)
1026 opset(ASUBE, r)
1027 opset(ASUBW, r)
1028 case ANEG:
1029 opset(ANEGW, r)
1030 case AFMOVD:
1031 opset(AFMOVS, r)
1032 case AMOVDBR:
1033 opset(AMOVWBR, r)
1034 case ACMP:
1035 opset(ACMPW, r)
1036 case ACMPU:
1037 opset(ACMPWU, r)
1038 case ATMHH:
1039 opset(ATMHL, r)
1040 opset(ATMLH, r)
1041 opset(ATMLL, r)
1042 case ACEFBRA:
1043 opset(ACDFBRA, r)
1044 opset(ACEGBRA, r)
1045 opset(ACDGBRA, r)
1046 opset(ACELFBR, r)
1047 opset(ACDLFBR, r)
1048 opset(ACELGBR, r)
1049 opset(ACDLGBR, r)
1050 case ACFEBRA:
1051 opset(ACFDBRA, r)
1052 opset(ACGEBRA, r)
1053 opset(ACGDBRA, r)
1054 opset(ACLFEBR, r)
1055 opset(ACLFDBR, r)
1056 opset(ACLGEBR, r)
1057 opset(ACLGDBR, r)
1058 case AFIEBR:
1059 opset(AFIDBR, r)
1060 case ACMPBEQ:
1061 opset(ACMPBGE, r)
1062 opset(ACMPBGT, r)
1063 opset(ACMPBLE, r)
1064 opset(ACMPBLT, r)
1065 opset(ACMPBNE, r)
1066 case ACMPUBEQ:
1067 opset(ACMPUBGE, r)
1068 opset(ACMPUBGT, r)
1069 opset(ACMPUBLE, r)
1070 opset(ACMPUBLT, r)
1071 opset(ACMPUBNE, r)
1072 case ACGRJ:
1073 opset(ACRJ, r)
1074 case ACLGRJ:
1075 opset(ACLRJ, r)
1076 case ACGIJ:
1077 opset(ACIJ, r)
1078 case ACLGIJ:
1079 opset(ACLIJ, r)
1080 case AMOVDEQ:
1081 opset(AMOVDGE, r)
1082 opset(AMOVDGT, r)
1083 opset(AMOVDLE, r)
1084 opset(AMOVDLT, r)
1085 opset(AMOVDNE, r)
1086 case ALOCGR:
1087 opset(ALOCR, r)
1088 case ALTDBR:
1089 opset(ALTEBR, r)
1090 case ATCDB:
1091 opset(ATCEB, r)
1092 case AVL:
1093 opset(AVLLEZB, r)
1094 opset(AVLLEZH, r)
1095 opset(AVLLEZF, r)
1096 opset(AVLLEZG, r)
1097 opset(AVLREPB, r)
1098 opset(AVLREPH, r)
1099 opset(AVLREPF, r)
1100 opset(AVLREPG, r)
1101 case AVLEG:
1102 opset(AVLBB, r)
1103 opset(AVLEB, r)
1104 opset(AVLEH, r)
1105 opset(AVLEF, r)
1106 opset(AVLEG, r)
1107 opset(AVLREP, r)
1108 case AVSTEG:
1109 opset(AVSTEB, r)
1110 opset(AVSTEH, r)
1111 opset(AVSTEF, r)
1112 case AVSCEG:
1113 opset(AVSCEF, r)
1114 case AVGEG:
1115 opset(AVGEF, r)
1116 case AVESLG:
1117 opset(AVESLB, r)
1118 opset(AVESLH, r)
1119 opset(AVESLF, r)
1120 opset(AVERLLB, r)
1121 opset(AVERLLH, r)
1122 opset(AVERLLF, r)
1123 opset(AVERLLG, r)
1124 opset(AVESRAB, r)
1125 opset(AVESRAH, r)
1126 opset(AVESRAF, r)
1127 opset(AVESRAG, r)
1128 opset(AVESRLB, r)
1129 opset(AVESRLH, r)
1130 opset(AVESRLF, r)
1131 opset(AVESRLG, r)
1132 case AVLGVG:
1133 opset(AVLGVB, r)
1134 opset(AVLGVH, r)
1135 opset(AVLGVF, r)
1136 case AVLVGG:
1137 opset(AVLVGB, r)
1138 opset(AVLVGH, r)
1139 opset(AVLVGF, r)
1140 case AVZERO:
1141 opset(AVONE, r)
1142 case AVREPIG:
1143 opset(AVREPIB, r)
1144 opset(AVREPIH, r)
1145 opset(AVREPIF, r)
1146 case AVLEIG:
1147 opset(AVLEIB, r)
1148 opset(AVLEIH, r)
1149 opset(AVLEIF, r)
1150 case AVGMG:
1151 opset(AVGMB, r)
1152 opset(AVGMH, r)
1153 opset(AVGMF, r)
1154 case AVREPG:
1155 opset(AVREPB, r)
1156 opset(AVREPH, r)
1157 opset(AVREPF, r)
1158 case AVERIMG:
1159 opset(AVERIMB, r)
1160 opset(AVERIMH, r)
1161 opset(AVERIMF, r)
1162 case AVFTCIDB:
1163 opset(AWFTCIDB, r)
1164 case AVLR:
1165 opset(AVUPHB, r)
1166 opset(AVUPHH, r)
1167 opset(AVUPHF, r)
1168 opset(AVUPLHB, r)
1169 opset(AVUPLHH, r)
1170 opset(AVUPLHF, r)
1171 opset(AVUPLB, r)
1172 opset(AVUPLHW, r)
1173 opset(AVUPLF, r)
1174 opset(AVUPLLB, r)
1175 opset(AVUPLLH, r)
1176 opset(AVUPLLF, r)
1177 opset(AVCLZB, r)
1178 opset(AVCLZH, r)
1179 opset(AVCLZF, r)
1180 opset(AVCLZG, r)
1181 opset(AVCTZB, r)
1182 opset(AVCTZH, r)
1183 opset(AVCTZF, r)
1184 opset(AVCTZG, r)
1185 opset(AVLDEB, r)
1186 opset(AWLDEB, r)
1187 opset(AVFLCDB, r)
1188 opset(AWFLCDB, r)
1189 opset(AVFLNDB, r)
1190 opset(AWFLNDB, r)
1191 opset(AVFLPDB, r)
1192 opset(AWFLPDB, r)
1193 opset(AVFSQDB, r)
1194 opset(AWFSQDB, r)
1195 opset(AVISTRB, r)
1196 opset(AVISTRH, r)
1197 opset(AVISTRF, r)
1198 opset(AVISTRBS, r)
1199 opset(AVISTRHS, r)
1200 opset(AVISTRFS, r)
1201 opset(AVLCB, r)
1202 opset(AVLCH, r)
1203 opset(AVLCF, r)
1204 opset(AVLCG, r)
1205 opset(AVLPB, r)
1206 opset(AVLPH, r)
1207 opset(AVLPF, r)
1208 opset(AVLPG, r)
1209 opset(AVPOPCT, r)
1210 opset(AVSEGB, r)
1211 opset(AVSEGH, r)
1212 opset(AVSEGF, r)
1213 case AVECG:
1214 opset(AVECB, r)
1215 opset(AVECH, r)
1216 opset(AVECF, r)
1217 opset(AVECLB, r)
1218 opset(AVECLH, r)
1219 opset(AVECLF, r)
1220 opset(AVECLG, r)
1221 opset(AWFCDB, r)
1222 opset(AWFKDB, r)
1223 case AVCEQG:
1224 opset(AVCEQB, r)
1225 opset(AVCEQH, r)
1226 opset(AVCEQF, r)
1227 opset(AVCEQBS, r)
1228 opset(AVCEQHS, r)
1229 opset(AVCEQFS, r)
1230 opset(AVCEQGS, r)
1231 opset(AVCHB, r)
1232 opset(AVCHH, r)
1233 opset(AVCHF, r)
1234 opset(AVCHG, r)
1235 opset(AVCHBS, r)
1236 opset(AVCHHS, r)
1237 opset(AVCHFS, r)
1238 opset(AVCHGS, r)
1239 opset(AVCHLB, r)
1240 opset(AVCHLH, r)
1241 opset(AVCHLF, r)
1242 opset(AVCHLG, r)
1243 opset(AVCHLBS, r)
1244 opset(AVCHLHS, r)
1245 opset(AVCHLFS, r)
1246 opset(AVCHLGS, r)
1247 case AVFAEF:
1248 opset(AVFAEB, r)
1249 opset(AVFAEH, r)
1250 opset(AVFAEBS, r)
1251 opset(AVFAEHS, r)
1252 opset(AVFAEFS, r)
1253 opset(AVFAEZB, r)
1254 opset(AVFAEZH, r)
1255 opset(AVFAEZF, r)
1256 opset(AVFAEZBS, r)
1257 opset(AVFAEZHS, r)
1258 opset(AVFAEZFS, r)
1259 opset(AVFEEB, r)
1260 opset(AVFEEH, r)
1261 opset(AVFEEF, r)
1262 opset(AVFEEBS, r)
1263 opset(AVFEEHS, r)
1264 opset(AVFEEFS, r)
1265 opset(AVFEEZB, r)
1266 opset(AVFEEZH, r)
1267 opset(AVFEEZF, r)
1268 opset(AVFEEZBS, r)
1269 opset(AVFEEZHS, r)
1270 opset(AVFEEZFS, r)
1271 opset(AVFENEB, r)
1272 opset(AVFENEH, r)
1273 opset(AVFENEF, r)
1274 opset(AVFENEBS, r)
1275 opset(AVFENEHS, r)
1276 opset(AVFENEFS, r)
1277 opset(AVFENEZB, r)
1278 opset(AVFENEZH, r)
1279 opset(AVFENEZF, r)
1280 opset(AVFENEZBS, r)
1281 opset(AVFENEZHS, r)
1282 opset(AVFENEZFS, r)
1283 case AVPKSG:
1284 opset(AVPKSH, r)
1285 opset(AVPKSF, r)
1286 opset(AVPKSHS, r)
1287 opset(AVPKSFS, r)
1288 opset(AVPKSGS, r)
1289 opset(AVPKLSH, r)
1290 opset(AVPKLSF, r)
1291 opset(AVPKLSG, r)
1292 opset(AVPKLSHS, r)
1293 opset(AVPKLSFS, r)
1294 opset(AVPKLSGS, r)
1295 case AVAQ:
1296 opset(AVAB, r)
1297 opset(AVAH, r)
1298 opset(AVAF, r)
1299 opset(AVAG, r)
1300 opset(AVACCB, r)
1301 opset(AVACCH, r)
1302 opset(AVACCF, r)
1303 opset(AVACCG, r)
1304 opset(AVACCQ, r)
1305 opset(AVN, r)
1306 opset(AVNC, r)
1307 opset(AVAVGB, r)
1308 opset(AVAVGH, r)
1309 opset(AVAVGF, r)
1310 opset(AVAVGG, r)
1311 opset(AVAVGLB, r)
1312 opset(AVAVGLH, r)
1313 opset(AVAVGLF, r)
1314 opset(AVAVGLG, r)
1315 opset(AVCKSM, r)
1316 opset(AVX, r)
1317 opset(AVFADB, r)
1318 opset(AWFADB, r)
1319 opset(AVFCEDB, r)
1320 opset(AVFCEDBS, r)
1321 opset(AWFCEDB, r)
1322 opset(AWFCEDBS, r)
1323 opset(AVFCHDB, r)
1324 opset(AVFCHDBS, r)
1325 opset(AWFCHDB, r)
1326 opset(AWFCHDBS, r)
1327 opset(AVFCHEDB, r)
1328 opset(AVFCHEDBS, r)
1329 opset(AWFCHEDB, r)
1330 opset(AWFCHEDBS, r)
1331 opset(AVFMDB, r)
1332 opset(AWFMDB, r)
1333 opset(AVGFMB, r)
1334 opset(AVGFMH, r)
1335 opset(AVGFMF, r)
1336 opset(AVGFMG, r)
1337 opset(AVMXB, r)
1338 opset(AVMXH, r)
1339 opset(AVMXF, r)
1340 opset(AVMXG, r)
1341 opset(AVMXLB, r)
1342 opset(AVMXLH, r)
1343 opset(AVMXLF, r)
1344 opset(AVMXLG, r)
1345 opset(AVMNB, r)
1346 opset(AVMNH, r)
1347 opset(AVMNF, r)
1348 opset(AVMNG, r)
1349 opset(AVMNLB, r)
1350 opset(AVMNLH, r)
1351 opset(AVMNLF, r)
1352 opset(AVMNLG, r)
1353 opset(AVMRHB, r)
1354 opset(AVMRHH, r)
1355 opset(AVMRHF, r)
1356 opset(AVMRHG, r)
1357 opset(AVMRLB, r)
1358 opset(AVMRLH, r)
1359 opset(AVMRLF, r)
1360 opset(AVMRLG, r)
1361 opset(AVMEB, r)
1362 opset(AVMEH, r)
1363 opset(AVMEF, r)
1364 opset(AVMLEB, r)
1365 opset(AVMLEH, r)
1366 opset(AVMLEF, r)
1367 opset(AVMOB, r)
1368 opset(AVMOH, r)
1369 opset(AVMOF, r)
1370 opset(AVMLOB, r)
1371 opset(AVMLOH, r)
1372 opset(AVMLOF, r)
1373 opset(AVMHB, r)
1374 opset(AVMHH, r)
1375 opset(AVMHF, r)
1376 opset(AVMLHB, r)
1377 opset(AVMLHH, r)
1378 opset(AVMLHF, r)
1379 opset(AVMLH, r)
1380 opset(AVMLHW, r)
1381 opset(AVMLF, r)
1382 opset(AVNO, r)
1383 opset(AVO, r)
1384 opset(AVPKH, r)
1385 opset(AVPKF, r)
1386 opset(AVPKG, r)
1387 opset(AVSUMGH, r)
1388 opset(AVSUMGF, r)
1389 opset(AVSUMQF, r)
1390 opset(AVSUMQG, r)
1391 opset(AVSUMB, r)
1392 opset(AVSUMH, r)
1393 case AVERLLVG:
1394 opset(AVERLLVB, r)
1395 opset(AVERLLVH, r)
1396 opset(AVERLLVF, r)
1397 opset(AVESLVB, r)
1398 opset(AVESLVH, r)
1399 opset(AVESLVF, r)
1400 opset(AVESLVG, r)
1401 opset(AVESRAVB, r)
1402 opset(AVESRAVH, r)
1403 opset(AVESRAVF, r)
1404 opset(AVESRAVG, r)
1405 opset(AVESRLVB, r)
1406 opset(AVESRLVH, r)
1407 opset(AVESRLVF, r)
1408 opset(AVESRLVG, r)
1409 opset(AVFDDB, r)
1410 opset(AWFDDB, r)
1411 opset(AVFSDB, r)
1412 opset(AWFSDB, r)
1413 opset(AVSL, r)
1414 opset(AVSLB, r)
1415 opset(AVSRA, r)
1416 opset(AVSRAB, r)
1417 opset(AVSRL, r)
1418 opset(AVSRLB, r)
1419 opset(AVSB, r)
1420 opset(AVSH, r)
1421 opset(AVSF, r)
1422 opset(AVSG, r)
1423 opset(AVSQ, r)
1424 opset(AVSCBIB, r)
1425 opset(AVSCBIH, r)
1426 opset(AVSCBIF, r)
1427 opset(AVSCBIG, r)
1428 opset(AVSCBIQ, r)
1429 case AVACQ:
1430 opset(AVACCCQ, r)
1431 opset(AVGFMAB, r)
1432 opset(AVGFMAH, r)
1433 opset(AVGFMAF, r)
1434 opset(AVGFMAG, r)
1435 opset(AVMALB, r)
1436 opset(AVMALHW, r)
1437 opset(AVMALF, r)
1438 opset(AVMAHB, r)
1439 opset(AVMAHH, r)
1440 opset(AVMAHF, r)
1441 opset(AVMALHB, r)
1442 opset(AVMALHH, r)
1443 opset(AVMALHF, r)
1444 opset(AVMAEB, r)
1445 opset(AVMAEH, r)
1446 opset(AVMAEF, r)
1447 opset(AVMALEB, r)
1448 opset(AVMALEH, r)
1449 opset(AVMALEF, r)
1450 opset(AVMAOB, r)
1451 opset(AVMAOH, r)
1452 opset(AVMAOF, r)
1453 opset(AVMALOB, r)
1454 opset(AVMALOH, r)
1455 opset(AVMALOF, r)
1456 opset(AVSTRCB, r)
1457 opset(AVSTRCH, r)
1458 opset(AVSTRCF, r)
1459 opset(AVSTRCBS, r)
1460 opset(AVSTRCHS, r)
1461 opset(AVSTRCFS, r)
1462 opset(AVSTRCZB, r)
1463 opset(AVSTRCZH, r)
1464 opset(AVSTRCZF, r)
1465 opset(AVSTRCZBS, r)
1466 opset(AVSTRCZHS, r)
1467 opset(AVSTRCZFS, r)
1468 opset(AVSBCBIQ, r)
1469 opset(AVSBIQ, r)
1470 opset(AVMSLG, r)
1471 opset(AVMSLEG, r)
1472 opset(AVMSLOG, r)
1473 opset(AVMSLEOG, r)
1474 case AVSEL:
1475 opset(AVFMADB, r)
1476 opset(AWFMADB, r)
1477 opset(AVFMSDB, r)
1478 opset(AWFMSDB, r)
1479 opset(AVPERM, r)
1480 }
1481 }
1482 }
1483
1484 const (
1485 op_A uint32 = 0x5A00
1486 op_AD uint32 = 0x6A00
1487 op_ADB uint32 = 0xED1A
1488 op_ADBR uint32 = 0xB31A
1489 op_ADR uint32 = 0x2A00
1490 op_ADTR uint32 = 0xB3D2
1491 op_ADTRA uint32 = 0xB3D2
1492 op_AE uint32 = 0x7A00
1493 op_AEB uint32 = 0xED0A
1494 op_AEBR uint32 = 0xB30A
1495 op_AER uint32 = 0x3A00
1496 op_AFI uint32 = 0xC209
1497 op_AG uint32 = 0xE308
1498 op_AGF uint32 = 0xE318
1499 op_AGFI uint32 = 0xC208
1500 op_AGFR uint32 = 0xB918
1501 op_AGHI uint32 = 0xA70B
1502 op_AGHIK uint32 = 0xECD9
1503 op_AGR uint32 = 0xB908
1504 op_AGRK uint32 = 0xB9E8
1505 op_AGSI uint32 = 0xEB7A
1506 op_AH uint32 = 0x4A00
1507 op_AHHHR uint32 = 0xB9C8
1508 op_AHHLR uint32 = 0xB9D8
1509 op_AHI uint32 = 0xA70A
1510 op_AHIK uint32 = 0xECD8
1511 op_AHY uint32 = 0xE37A
1512 op_AIH uint32 = 0xCC08
1513 op_AL uint32 = 0x5E00
1514 op_ALC uint32 = 0xE398
1515 op_ALCG uint32 = 0xE388
1516 op_ALCGR uint32 = 0xB988
1517 op_ALCR uint32 = 0xB998
1518 op_ALFI uint32 = 0xC20B
1519 op_ALG uint32 = 0xE30A
1520 op_ALGF uint32 = 0xE31A
1521 op_ALGFI uint32 = 0xC20A
1522 op_ALGFR uint32 = 0xB91A
1523 op_ALGHSIK uint32 = 0xECDB
1524 op_ALGR uint32 = 0xB90A
1525 op_ALGRK uint32 = 0xB9EA
1526 op_ALGSI uint32 = 0xEB7E
1527 op_ALHHHR uint32 = 0xB9CA
1528 op_ALHHLR uint32 = 0xB9DA
1529 op_ALHSIK uint32 = 0xECDA
1530 op_ALR uint32 = 0x1E00
1531 op_ALRK uint32 = 0xB9FA
1532 op_ALSI uint32 = 0xEB6E
1533 op_ALSIH uint32 = 0xCC0A
1534 op_ALSIHN uint32 = 0xCC0B
1535 op_ALY uint32 = 0xE35E
1536 op_AP uint32 = 0xFA00
1537 op_AR uint32 = 0x1A00
1538 op_ARK uint32 = 0xB9F8
1539 op_ASI uint32 = 0xEB6A
1540 op_AU uint32 = 0x7E00
1541 op_AUR uint32 = 0x3E00
1542 op_AW uint32 = 0x6E00
1543 op_AWR uint32 = 0x2E00
1544 op_AXBR uint32 = 0xB34A
1545 op_AXR uint32 = 0x3600
1546 op_AXTR uint32 = 0xB3DA
1547 op_AXTRA uint32 = 0xB3DA
1548 op_AY uint32 = 0xE35A
1549 op_BAKR uint32 = 0xB240
1550 op_BAL uint32 = 0x4500
1551 op_BALR uint32 = 0x0500
1552 op_BAS uint32 = 0x4D00
1553 op_BASR uint32 = 0x0D00
1554 op_BASSM uint32 = 0x0C00
1555 op_BC uint32 = 0x4700
1556 op_BCR uint32 = 0x0700
1557 op_BCT uint32 = 0x4600
1558 op_BCTG uint32 = 0xE346
1559 op_BCTGR uint32 = 0xB946
1560 op_BCTR uint32 = 0x0600
1561 op_BPP uint32 = 0xC700
1562 op_BPRP uint32 = 0xC500
1563 op_BRAS uint32 = 0xA705
1564 op_BRASL uint32 = 0xC005
1565 op_BRC uint32 = 0xA704
1566 op_BRCL uint32 = 0xC004
1567 op_BRCT uint32 = 0xA706
1568 op_BRCTG uint32 = 0xA707
1569 op_BRCTH uint32 = 0xCC06
1570 op_BRXH uint32 = 0x8400
1571 op_BRXHG uint32 = 0xEC44
1572 op_BRXLE uint32 = 0x8500
1573 op_BRXLG uint32 = 0xEC45
1574 op_BSA uint32 = 0xB25A
1575 op_BSG uint32 = 0xB258
1576 op_BSM uint32 = 0x0B00
1577 op_BXH uint32 = 0x8600
1578 op_BXHG uint32 = 0xEB44
1579 op_BXLE uint32 = 0x8700
1580 op_BXLEG uint32 = 0xEB45
1581 op_C uint32 = 0x5900
1582 op_CD uint32 = 0x6900
1583 op_CDB uint32 = 0xED19
1584 op_CDBR uint32 = 0xB319
1585 op_CDFBR uint32 = 0xB395
1586 op_CDFBRA uint32 = 0xB395
1587 op_CDFR uint32 = 0xB3B5
1588 op_CDFTR uint32 = 0xB951
1589 op_CDGBR uint32 = 0xB3A5
1590 op_CDGBRA uint32 = 0xB3A5
1591 op_CDGR uint32 = 0xB3C5
1592 op_CDGTR uint32 = 0xB3F1
1593 op_CDGTRA uint32 = 0xB3F1
1594 op_CDLFBR uint32 = 0xB391
1595 op_CDLFTR uint32 = 0xB953
1596 op_CDLGBR uint32 = 0xB3A1
1597 op_CDLGTR uint32 = 0xB952
1598 op_CDR uint32 = 0x2900
1599 op_CDS uint32 = 0xBB00
1600 op_CDSG uint32 = 0xEB3E
1601 op_CDSTR uint32 = 0xB3F3
1602 op_CDSY uint32 = 0xEB31
1603 op_CDTR uint32 = 0xB3E4
1604 op_CDUTR uint32 = 0xB3F2
1605 op_CDZT uint32 = 0xEDAA
1606 op_CE uint32 = 0x7900
1607 op_CEB uint32 = 0xED09
1608 op_CEBR uint32 = 0xB309
1609 op_CEDTR uint32 = 0xB3F4
1610 op_CEFBR uint32 = 0xB394
1611 op_CEFBRA uint32 = 0xB394
1612 op_CEFR uint32 = 0xB3B4
1613 op_CEGBR uint32 = 0xB3A4
1614 op_CEGBRA uint32 = 0xB3A4
1615 op_CEGR uint32 = 0xB3C4
1616 op_CELFBR uint32 = 0xB390
1617 op_CELGBR uint32 = 0xB3A0
1618 op_CER uint32 = 0x3900
1619 op_CEXTR uint32 = 0xB3FC
1620 op_CFC uint32 = 0xB21A
1621 op_CFDBR uint32 = 0xB399
1622 op_CFDBRA uint32 = 0xB399
1623 op_CFDR uint32 = 0xB3B9
1624 op_CFDTR uint32 = 0xB941
1625 op_CFEBR uint32 = 0xB398
1626 op_CFEBRA uint32 = 0xB398
1627 op_CFER uint32 = 0xB3B8
1628 op_CFI uint32 = 0xC20D
1629 op_CFXBR uint32 = 0xB39A
1630 op_CFXBRA uint32 = 0xB39A
1631 op_CFXR uint32 = 0xB3BA
1632 op_CFXTR uint32 = 0xB949
1633 op_CG uint32 = 0xE320
1634 op_CGDBR uint32 = 0xB3A9
1635 op_CGDBRA uint32 = 0xB3A9
1636 op_CGDR uint32 = 0xB3C9
1637 op_CGDTR uint32 = 0xB3E1
1638 op_CGDTRA uint32 = 0xB3E1
1639 op_CGEBR uint32 = 0xB3A8
1640 op_CGEBRA uint32 = 0xB3A8
1641 op_CGER uint32 = 0xB3C8
1642 op_CGF uint32 = 0xE330
1643 op_CGFI uint32 = 0xC20C
1644 op_CGFR uint32 = 0xB930
1645 op_CGFRL uint32 = 0xC60C
1646 op_CGH uint32 = 0xE334
1647 op_CGHI uint32 = 0xA70F
1648 op_CGHRL uint32 = 0xC604
1649 op_CGHSI uint32 = 0xE558
1650 op_CGIB uint32 = 0xECFC
1651 op_CGIJ uint32 = 0xEC7C
1652 op_CGIT uint32 = 0xEC70
1653 op_CGR uint32 = 0xB920
1654 op_CGRB uint32 = 0xECE4
1655 op_CGRJ uint32 = 0xEC64
1656 op_CGRL uint32 = 0xC608
1657 op_CGRT uint32 = 0xB960
1658 op_CGXBR uint32 = 0xB3AA
1659 op_CGXBRA uint32 = 0xB3AA
1660 op_CGXR uint32 = 0xB3CA
1661 op_CGXTR uint32 = 0xB3E9
1662 op_CGXTRA uint32 = 0xB3E9
1663 op_CH uint32 = 0x4900
1664 op_CHF uint32 = 0xE3CD
1665 op_CHHR uint32 = 0xB9CD
1666 op_CHHSI uint32 = 0xE554
1667 op_CHI uint32 = 0xA70E
1668 op_CHLR uint32 = 0xB9DD
1669 op_CHRL uint32 = 0xC605
1670 op_CHSI uint32 = 0xE55C
1671 op_CHY uint32 = 0xE379
1672 op_CIB uint32 = 0xECFE
1673 op_CIH uint32 = 0xCC0D
1674 op_CIJ uint32 = 0xEC7E
1675 op_CIT uint32 = 0xEC72
1676 op_CKSM uint32 = 0xB241
1677 op_CL uint32 = 0x5500
1678 op_CLC uint32 = 0xD500
1679 op_CLCL uint32 = 0x0F00
1680 op_CLCLE uint32 = 0xA900
1681 op_CLCLU uint32 = 0xEB8F
1682 op_CLFDBR uint32 = 0xB39D
1683 op_CLFDTR uint32 = 0xB943
1684 op_CLFEBR uint32 = 0xB39C
1685 op_CLFHSI uint32 = 0xE55D
1686 op_CLFI uint32 = 0xC20F
1687 op_CLFIT uint32 = 0xEC73
1688 op_CLFXBR uint32 = 0xB39E
1689 op_CLFXTR uint32 = 0xB94B
1690 op_CLG uint32 = 0xE321
1691 op_CLGDBR uint32 = 0xB3AD
1692 op_CLGDTR uint32 = 0xB942
1693 op_CLGEBR uint32 = 0xB3AC
1694 op_CLGF uint32 = 0xE331
1695 op_CLGFI uint32 = 0xC20E
1696 op_CLGFR uint32 = 0xB931
1697 op_CLGFRL uint32 = 0xC60E
1698 op_CLGHRL uint32 = 0xC606
1699 op_CLGHSI uint32 = 0xE559
1700 op_CLGIB uint32 = 0xECFD
1701 op_CLGIJ uint32 = 0xEC7D
1702 op_CLGIT uint32 = 0xEC71
1703 op_CLGR uint32 = 0xB921
1704 op_CLGRB uint32 = 0xECE5
1705 op_CLGRJ uint32 = 0xEC65
1706 op_CLGRL uint32 = 0xC60A
1707 op_CLGRT uint32 = 0xB961
1708 op_CLGT uint32 = 0xEB2B
1709 op_CLGXBR uint32 = 0xB3AE
1710 op_CLGXTR uint32 = 0xB94A
1711 op_CLHF uint32 = 0xE3CF
1712 op_CLHHR uint32 = 0xB9CF
1713 op_CLHHSI uint32 = 0xE555
1714 op_CLHLR uint32 = 0xB9DF
1715 op_CLHRL uint32 = 0xC607
1716 op_CLI uint32 = 0x9500
1717 op_CLIB uint32 = 0xECFF
1718 op_CLIH uint32 = 0xCC0F
1719 op_CLIJ uint32 = 0xEC7F
1720 op_CLIY uint32 = 0xEB55
1721 op_CLM uint32 = 0xBD00
1722 op_CLMH uint32 = 0xEB20
1723 op_CLMY uint32 = 0xEB21
1724 op_CLR uint32 = 0x1500
1725 op_CLRB uint32 = 0xECF7
1726 op_CLRJ uint32 = 0xEC77
1727 op_CLRL uint32 = 0xC60F
1728 op_CLRT uint32 = 0xB973
1729 op_CLST uint32 = 0xB25D
1730 op_CLT uint32 = 0xEB23
1731 op_CLY uint32 = 0xE355
1732 op_CMPSC uint32 = 0xB263
1733 op_CP uint32 = 0xF900
1734 op_CPSDR uint32 = 0xB372
1735 op_CPYA uint32 = 0xB24D
1736 op_CR uint32 = 0x1900
1737 op_CRB uint32 = 0xECF6
1738 op_CRDTE uint32 = 0xB98F
1739 op_CRJ uint32 = 0xEC76
1740 op_CRL uint32 = 0xC60D
1741 op_CRT uint32 = 0xB972
1742 op_CS uint32 = 0xBA00
1743 op_CSCH uint32 = 0xB230
1744 op_CSDTR uint32 = 0xB3E3
1745 op_CSG uint32 = 0xEB30
1746 op_CSP uint32 = 0xB250
1747 op_CSPG uint32 = 0xB98A
1748 op_CSST uint32 = 0xC802
1749 op_CSXTR uint32 = 0xB3EB
1750 op_CSY uint32 = 0xEB14
1751 op_CU12 uint32 = 0xB2A7
1752 op_CU14 uint32 = 0xB9B0
1753 op_CU21 uint32 = 0xB2A6
1754 op_CU24 uint32 = 0xB9B1
1755 op_CU41 uint32 = 0xB9B2
1756 op_CU42 uint32 = 0xB9B3
1757 op_CUDTR uint32 = 0xB3E2
1758 op_CUSE uint32 = 0xB257
1759 op_CUTFU uint32 = 0xB2A7
1760 op_CUUTF uint32 = 0xB2A6
1761 op_CUXTR uint32 = 0xB3EA
1762 op_CVB uint32 = 0x4F00
1763 op_CVBG uint32 = 0xE30E
1764 op_CVBY uint32 = 0xE306
1765 op_CVD uint32 = 0x4E00
1766 op_CVDG uint32 = 0xE32E
1767 op_CVDY uint32 = 0xE326
1768 op_CXBR uint32 = 0xB349
1769 op_CXFBR uint32 = 0xB396
1770 op_CXFBRA uint32 = 0xB396
1771 op_CXFR uint32 = 0xB3B6
1772 op_CXFTR uint32 = 0xB959
1773 op_CXGBR uint32 = 0xB3A6
1774 op_CXGBRA uint32 = 0xB3A6
1775 op_CXGR uint32 = 0xB3C6
1776 op_CXGTR uint32 = 0xB3F9
1777 op_CXGTRA uint32 = 0xB3F9
1778 op_CXLFBR uint32 = 0xB392
1779 op_CXLFTR uint32 = 0xB95B
1780 op_CXLGBR uint32 = 0xB3A2
1781 op_CXLGTR uint32 = 0xB95A
1782 op_CXR uint32 = 0xB369
1783 op_CXSTR uint32 = 0xB3FB
1784 op_CXTR uint32 = 0xB3EC
1785 op_CXUTR uint32 = 0xB3FA
1786 op_CXZT uint32 = 0xEDAB
1787 op_CY uint32 = 0xE359
1788 op_CZDT uint32 = 0xEDA8
1789 op_CZXT uint32 = 0xEDA9
1790 op_D uint32 = 0x5D00
1791 op_DD uint32 = 0x6D00
1792 op_DDB uint32 = 0xED1D
1793 op_DDBR uint32 = 0xB31D
1794 op_DDR uint32 = 0x2D00
1795 op_DDTR uint32 = 0xB3D1
1796 op_DDTRA uint32 = 0xB3D1
1797 op_DE uint32 = 0x7D00
1798 op_DEB uint32 = 0xED0D
1799 op_DEBR uint32 = 0xB30D
1800 op_DER uint32 = 0x3D00
1801 op_DIDBR uint32 = 0xB35B
1802 op_DIEBR uint32 = 0xB353
1803 op_DL uint32 = 0xE397
1804 op_DLG uint32 = 0xE387
1805 op_DLGR uint32 = 0xB987
1806 op_DLR uint32 = 0xB997
1807 op_DP uint32 = 0xFD00
1808 op_DR uint32 = 0x1D00
1809 op_DSG uint32 = 0xE30D
1810 op_DSGF uint32 = 0xE31D
1811 op_DSGFR uint32 = 0xB91D
1812 op_DSGR uint32 = 0xB90D
1813 op_DXBR uint32 = 0xB34D
1814 op_DXR uint32 = 0xB22D
1815 op_DXTR uint32 = 0xB3D9
1816 op_DXTRA uint32 = 0xB3D9
1817 op_EAR uint32 = 0xB24F
1818 op_ECAG uint32 = 0xEB4C
1819 op_ECTG uint32 = 0xC801
1820 op_ED uint32 = 0xDE00
1821 op_EDMK uint32 = 0xDF00
1822 op_EEDTR uint32 = 0xB3E5
1823 op_EEXTR uint32 = 0xB3ED
1824 op_EFPC uint32 = 0xB38C
1825 op_EPAIR uint32 = 0xB99A
1826 op_EPAR uint32 = 0xB226
1827 op_EPSW uint32 = 0xB98D
1828 op_EREG uint32 = 0xB249
1829 op_EREGG uint32 = 0xB90E
1830 op_ESAIR uint32 = 0xB99B
1831 op_ESAR uint32 = 0xB227
1832 op_ESDTR uint32 = 0xB3E7
1833 op_ESEA uint32 = 0xB99D
1834 op_ESTA uint32 = 0xB24A
1835 op_ESXTR uint32 = 0xB3EF
1836 op_ETND uint32 = 0xB2EC
1837 op_EX uint32 = 0x4400
1838 op_EXRL uint32 = 0xC600
1839 op_FIDBR uint32 = 0xB35F
1840 op_FIDBRA uint32 = 0xB35F
1841 op_FIDR uint32 = 0xB37F
1842 op_FIDTR uint32 = 0xB3D7
1843 op_FIEBR uint32 = 0xB357
1844 op_FIEBRA uint32 = 0xB357
1845 op_FIER uint32 = 0xB377
1846 op_FIXBR uint32 = 0xB347
1847 op_FIXBRA uint32 = 0xB347
1848 op_FIXR uint32 = 0xB367
1849 op_FIXTR uint32 = 0xB3DF
1850 op_FLOGR uint32 = 0xB983
1851 op_HDR uint32 = 0x2400
1852 op_HER uint32 = 0x3400
1853 op_HSCH uint32 = 0xB231
1854 op_IAC uint32 = 0xB224
1855 op_IC uint32 = 0x4300
1856 op_ICM uint32 = 0xBF00
1857 op_ICMH uint32 = 0xEB80
1858 op_ICMY uint32 = 0xEB81
1859 op_ICY uint32 = 0xE373
1860 op_IDTE uint32 = 0xB98E
1861 op_IEDTR uint32 = 0xB3F6
1862 op_IEXTR uint32 = 0xB3FE
1863 op_IIHF uint32 = 0xC008
1864 op_IIHH uint32 = 0xA500
1865 op_IIHL uint32 = 0xA501
1866 op_IILF uint32 = 0xC009
1867 op_IILH uint32 = 0xA502
1868 op_IILL uint32 = 0xA503
1869 op_IPK uint32 = 0xB20B
1870 op_IPM uint32 = 0xB222
1871 op_IPTE uint32 = 0xB221
1872 op_ISKE uint32 = 0xB229
1873 op_IVSK uint32 = 0xB223
1874 op_KDB uint32 = 0xED18
1875 op_KDBR uint32 = 0xB318
1876 op_KDTR uint32 = 0xB3E0
1877 op_KEB uint32 = 0xED08
1878 op_KEBR uint32 = 0xB308
1879 op_KIMD uint32 = 0xB93E
1880 op_KLMD uint32 = 0xB93F
1881 op_KM uint32 = 0xB92E
1882 op_KMAC uint32 = 0xB91E
1883 op_KMC uint32 = 0xB92F
1884 op_KMCTR uint32 = 0xB92D
1885 op_KMF uint32 = 0xB92A
1886 op_KMO uint32 = 0xB92B
1887 op_KXBR uint32 = 0xB348
1888 op_KXTR uint32 = 0xB3E8
1889 op_L uint32 = 0x5800
1890 op_LA uint32 = 0x4100
1891 op_LAA uint32 = 0xEBF8
1892 op_LAAG uint32 = 0xEBE8
1893 op_LAAL uint32 = 0xEBFA
1894 op_LAALG uint32 = 0xEBEA
1895 op_LAE uint32 = 0x5100
1896 op_LAEY uint32 = 0xE375
1897 op_LAM uint32 = 0x9A00
1898 op_LAMY uint32 = 0xEB9A
1899 op_LAN uint32 = 0xEBF4
1900 op_LANG uint32 = 0xEBE4
1901 op_LAO uint32 = 0xEBF6
1902 op_LAOG uint32 = 0xEBE6
1903 op_LARL uint32 = 0xC000
1904 op_LASP uint32 = 0xE500
1905 op_LAT uint32 = 0xE39F
1906 op_LAX uint32 = 0xEBF7
1907 op_LAXG uint32 = 0xEBE7
1908 op_LAY uint32 = 0xE371
1909 op_LB uint32 = 0xE376
1910 op_LBH uint32 = 0xE3C0
1911 op_LBR uint32 = 0xB926
1912 op_LCDBR uint32 = 0xB313
1913 op_LCDFR uint32 = 0xB373
1914 op_LCDR uint32 = 0x2300
1915 op_LCEBR uint32 = 0xB303
1916 op_LCER uint32 = 0x3300
1917 op_LCGFR uint32 = 0xB913
1918 op_LCGR uint32 = 0xB903
1919 op_LCR uint32 = 0x1300
1920 op_LCTL uint32 = 0xB700
1921 op_LCTLG uint32 = 0xEB2F
1922 op_LCXBR uint32 = 0xB343
1923 op_LCXR uint32 = 0xB363
1924 op_LD uint32 = 0x6800
1925 op_LDE uint32 = 0xED24
1926 op_LDEB uint32 = 0xED04
1927 op_LDEBR uint32 = 0xB304
1928 op_LDER uint32 = 0xB324
1929 op_LDETR uint32 = 0xB3D4
1930 op_LDGR uint32 = 0xB3C1
1931 op_LDR uint32 = 0x2800
1932 op_LDXBR uint32 = 0xB345
1933 op_LDXBRA uint32 = 0xB345
1934 op_LDXR uint32 = 0x2500
1935 op_LDXTR uint32 = 0xB3DD
1936 op_LDY uint32 = 0xED65
1937 op_LE uint32 = 0x7800
1938 op_LEDBR uint32 = 0xB344
1939 op_LEDBRA uint32 = 0xB344
1940 op_LEDR uint32 = 0x3500
1941 op_LEDTR uint32 = 0xB3D5
1942 op_LER uint32 = 0x3800
1943 op_LEXBR uint32 = 0xB346
1944 op_LEXBRA uint32 = 0xB346
1945 op_LEXR uint32 = 0xB366
1946 op_LEY uint32 = 0xED64
1947 op_LFAS uint32 = 0xB2BD
1948 op_LFH uint32 = 0xE3CA
1949 op_LFHAT uint32 = 0xE3C8
1950 op_LFPC uint32 = 0xB29D
1951 op_LG uint32 = 0xE304
1952 op_LGAT uint32 = 0xE385
1953 op_LGB uint32 = 0xE377
1954 op_LGBR uint32 = 0xB906
1955 op_LGDR uint32 = 0xB3CD
1956 op_LGF uint32 = 0xE314
1957 op_LGFI uint32 = 0xC001
1958 op_LGFR uint32 = 0xB914
1959 op_LGFRL uint32 = 0xC40C
1960 op_LGH uint32 = 0xE315
1961 op_LGHI uint32 = 0xA709
1962 op_LGHR uint32 = 0xB907
1963 op_LGHRL uint32 = 0xC404
1964 op_LGR uint32 = 0xB904
1965 op_LGRL uint32 = 0xC408
1966 op_LH uint32 = 0x4800
1967 op_LHH uint32 = 0xE3C4
1968 op_LHI uint32 = 0xA708
1969 op_LHR uint32 = 0xB927
1970 op_LHRL uint32 = 0xC405
1971 op_LHY uint32 = 0xE378
1972 op_LLC uint32 = 0xE394
1973 op_LLCH uint32 = 0xE3C2
1974 op_LLCR uint32 = 0xB994
1975 op_LLGC uint32 = 0xE390
1976 op_LLGCR uint32 = 0xB984
1977 op_LLGF uint32 = 0xE316
1978 op_LLGFAT uint32 = 0xE39D
1979 op_LLGFR uint32 = 0xB916
1980 op_LLGFRL uint32 = 0xC40E
1981 op_LLGH uint32 = 0xE391
1982 op_LLGHR uint32 = 0xB985
1983 op_LLGHRL uint32 = 0xC406
1984 op_LLGT uint32 = 0xE317
1985 op_LLGTAT uint32 = 0xE39C
1986 op_LLGTR uint32 = 0xB917
1987 op_LLH uint32 = 0xE395
1988 op_LLHH uint32 = 0xE3C6
1989 op_LLHR uint32 = 0xB995
1990 op_LLHRL uint32 = 0xC402
1991 op_LLIHF uint32 = 0xC00E
1992 op_LLIHH uint32 = 0xA50C
1993 op_LLIHL uint32 = 0xA50D
1994 op_LLILF uint32 = 0xC00F
1995 op_LLILH uint32 = 0xA50E
1996 op_LLILL uint32 = 0xA50F
1997 op_LM uint32 = 0x9800
1998 op_LMD uint32 = 0xEF00
1999 op_LMG uint32 = 0xEB04
2000 op_LMH uint32 = 0xEB96
2001 op_LMY uint32 = 0xEB98
2002 op_LNDBR uint32 = 0xB311
2003 op_LNDFR uint32 = 0xB371
2004 op_LNDR uint32 = 0x2100
2005 op_LNEBR uint32 = 0xB301
2006 op_LNER uint32 = 0x3100
2007 op_LNGFR uint32 = 0xB911
2008 op_LNGR uint32 = 0xB901
2009 op_LNR uint32 = 0x1100
2010 op_LNXBR uint32 = 0xB341
2011 op_LNXR uint32 = 0xB361
2012 op_LOC uint32 = 0xEBF2
2013 op_LOCG uint32 = 0xEBE2
2014 op_LOCGR uint32 = 0xB9E2
2015 op_LOCR uint32 = 0xB9F2
2016 op_LPD uint32 = 0xC804
2017 op_LPDBR uint32 = 0xB310
2018 op_LPDFR uint32 = 0xB370
2019 op_LPDG uint32 = 0xC805
2020 op_LPDR uint32 = 0x2000
2021 op_LPEBR uint32 = 0xB300
2022 op_LPER uint32 = 0x3000
2023 op_LPGFR uint32 = 0xB910
2024 op_LPGR uint32 = 0xB900
2025 op_LPQ uint32 = 0xE38F
2026 op_LPR uint32 = 0x1000
2027 op_LPSW uint32 = 0x8200
2028 op_LPSWE uint32 = 0xB2B2
2029 op_LPTEA uint32 = 0xB9AA
2030 op_LPXBR uint32 = 0xB340
2031 op_LPXR uint32 = 0xB360
2032 op_LR uint32 = 0x1800
2033 op_LRA uint32 = 0xB100
2034 op_LRAG uint32 = 0xE303
2035 op_LRAY uint32 = 0xE313
2036 op_LRDR uint32 = 0x2500
2037 op_LRER uint32 = 0x3500
2038 op_LRL uint32 = 0xC40D
2039 op_LRV uint32 = 0xE31E
2040 op_LRVG uint32 = 0xE30F
2041 op_LRVGR uint32 = 0xB90F
2042 op_LRVH uint32 = 0xE31F
2043 op_LRVR uint32 = 0xB91F
2044 op_LT uint32 = 0xE312
2045 op_LTDBR uint32 = 0xB312
2046 op_LTDR uint32 = 0x2200
2047 op_LTDTR uint32 = 0xB3D6
2048 op_LTEBR uint32 = 0xB302
2049 op_LTER uint32 = 0x3200
2050 op_LTG uint32 = 0xE302
2051 op_LTGF uint32 = 0xE332
2052 op_LTGFR uint32 = 0xB912
2053 op_LTGR uint32 = 0xB902
2054 op_LTR uint32 = 0x1200
2055 op_LTXBR uint32 = 0xB342
2056 op_LTXR uint32 = 0xB362
2057 op_LTXTR uint32 = 0xB3DE
2058 op_LURA uint32 = 0xB24B
2059 op_LURAG uint32 = 0xB905
2060 op_LXD uint32 = 0xED25
2061 op_LXDB uint32 = 0xED05
2062 op_LXDBR uint32 = 0xB305
2063 op_LXDR uint32 = 0xB325
2064 op_LXDTR uint32 = 0xB3DC
2065 op_LXE uint32 = 0xED26
2066 op_LXEB uint32 = 0xED06
2067 op_LXEBR uint32 = 0xB306
2068 op_LXER uint32 = 0xB326
2069 op_LXR uint32 = 0xB365
2070 op_LY uint32 = 0xE358
2071 op_LZDR uint32 = 0xB375
2072 op_LZER uint32 = 0xB374
2073 op_LZXR uint32 = 0xB376
2074 op_M uint32 = 0x5C00
2075 op_MAD uint32 = 0xED3E
2076 op_MADB uint32 = 0xED1E
2077 op_MADBR uint32 = 0xB31E
2078 op_MADR uint32 = 0xB33E
2079 op_MAE uint32 = 0xED2E
2080 op_MAEB uint32 = 0xED0E
2081 op_MAEBR uint32 = 0xB30E
2082 op_MAER uint32 = 0xB32E
2083 op_MAY uint32 = 0xED3A
2084 op_MAYH uint32 = 0xED3C
2085 op_MAYHR uint32 = 0xB33C
2086 op_MAYL uint32 = 0xED38
2087 op_MAYLR uint32 = 0xB338
2088 op_MAYR uint32 = 0xB33A
2089 op_MC uint32 = 0xAF00
2090 op_MD uint32 = 0x6C00
2091 op_MDB uint32 = 0xED1C
2092 op_MDBR uint32 = 0xB31C
2093 op_MDE uint32 = 0x7C00
2094 op_MDEB uint32 = 0xED0C
2095 op_MDEBR uint32 = 0xB30C
2096 op_MDER uint32 = 0x3C00
2097 op_MDR uint32 = 0x2C00
2098 op_MDTR uint32 = 0xB3D0
2099 op_MDTRA uint32 = 0xB3D0
2100 op_ME uint32 = 0x7C00
2101 op_MEE uint32 = 0xED37
2102 op_MEEB uint32 = 0xED17
2103 op_MEEBR uint32 = 0xB317
2104 op_MEER uint32 = 0xB337
2105 op_MER uint32 = 0x3C00
2106 op_MFY uint32 = 0xE35C
2107 op_MGHI uint32 = 0xA70D
2108 op_MH uint32 = 0x4C00
2109 op_MHI uint32 = 0xA70C
2110 op_MHY uint32 = 0xE37C
2111 op_ML uint32 = 0xE396
2112 op_MLG uint32 = 0xE386
2113 op_MLGR uint32 = 0xB986
2114 op_MLR uint32 = 0xB996
2115 op_MP uint32 = 0xFC00
2116 op_MR uint32 = 0x1C00
2117 op_MS uint32 = 0x7100
2118 op_MSCH uint32 = 0xB232
2119 op_MSD uint32 = 0xED3F
2120 op_MSDB uint32 = 0xED1F
2121 op_MSDBR uint32 = 0xB31F
2122 op_MSDR uint32 = 0xB33F
2123 op_MSE uint32 = 0xED2F
2124 op_MSEB uint32 = 0xED0F
2125 op_MSEBR uint32 = 0xB30F
2126 op_MSER uint32 = 0xB32F
2127 op_MSFI uint32 = 0xC201
2128 op_MSG uint32 = 0xE30C
2129 op_MSGF uint32 = 0xE31C
2130 op_MSGFI uint32 = 0xC200
2131 op_MSGFR uint32 = 0xB91C
2132 op_MSGR uint32 = 0xB90C
2133 op_MSR uint32 = 0xB252
2134 op_MSTA uint32 = 0xB247
2135 op_MSY uint32 = 0xE351
2136 op_MVC uint32 = 0xD200
2137 op_MVCDK uint32 = 0xE50F
2138 op_MVCIN uint32 = 0xE800
2139 op_MVCK uint32 = 0xD900
2140 op_MVCL uint32 = 0x0E00
2141 op_MVCLE uint32 = 0xA800
2142 op_MVCLU uint32 = 0xEB8E
2143 op_MVCOS uint32 = 0xC800
2144 op_MVCP uint32 = 0xDA00
2145 op_MVCS uint32 = 0xDB00
2146 op_MVCSK uint32 = 0xE50E
2147 op_MVGHI uint32 = 0xE548
2148 op_MVHHI uint32 = 0xE544
2149 op_MVHI uint32 = 0xE54C
2150 op_MVI uint32 = 0x9200
2151 op_MVIY uint32 = 0xEB52
2152 op_MVN uint32 = 0xD100
2153 op_MVO uint32 = 0xF100
2154 op_MVPG uint32 = 0xB254
2155 op_MVST uint32 = 0xB255
2156 op_MVZ uint32 = 0xD300
2157 op_MXBR uint32 = 0xB34C
2158 op_MXD uint32 = 0x6700
2159 op_MXDB uint32 = 0xED07
2160 op_MXDBR uint32 = 0xB307
2161 op_MXDR uint32 = 0x2700
2162 op_MXR uint32 = 0x2600
2163 op_MXTR uint32 = 0xB3D8
2164 op_MXTRA uint32 = 0xB3D8
2165 op_MY uint32 = 0xED3B
2166 op_MYH uint32 = 0xED3D
2167 op_MYHR uint32 = 0xB33D
2168 op_MYL uint32 = 0xED39
2169 op_MYLR uint32 = 0xB339
2170 op_MYR uint32 = 0xB33B
2171 op_N uint32 = 0x5400
2172 op_NC uint32 = 0xD400
2173 op_NG uint32 = 0xE380
2174 op_NGR uint32 = 0xB980
2175 op_NGRK uint32 = 0xB9E4
2176 op_NI uint32 = 0x9400
2177 op_NIAI uint32 = 0xB2FA
2178 op_NIHF uint32 = 0xC00A
2179 op_NIHH uint32 = 0xA504
2180 op_NIHL uint32 = 0xA505
2181 op_NILF uint32 = 0xC00B
2182 op_NILH uint32 = 0xA506
2183 op_NILL uint32 = 0xA507
2184 op_NIY uint32 = 0xEB54
2185 op_NR uint32 = 0x1400
2186 op_NRK uint32 = 0xB9F4
2187 op_NTSTG uint32 = 0xE325
2188 op_NY uint32 = 0xE354
2189 op_O uint32 = 0x5600
2190 op_OC uint32 = 0xD600
2191 op_OG uint32 = 0xE381
2192 op_OGR uint32 = 0xB981
2193 op_OGRK uint32 = 0xB9E6
2194 op_OI uint32 = 0x9600
2195 op_OIHF uint32 = 0xC00C
2196 op_OIHH uint32 = 0xA508
2197 op_OIHL uint32 = 0xA509
2198 op_OILF uint32 = 0xC00D
2199 op_OILH uint32 = 0xA50A
2200 op_OILL uint32 = 0xA50B
2201 op_OIY uint32 = 0xEB56
2202 op_OR uint32 = 0x1600
2203 op_ORK uint32 = 0xB9F6
2204 op_OY uint32 = 0xE356
2205 op_PACK uint32 = 0xF200
2206 op_PALB uint32 = 0xB248
2207 op_PC uint32 = 0xB218
2208 op_PCC uint32 = 0xB92C
2209 op_PCKMO uint32 = 0xB928
2210 op_PFD uint32 = 0xE336
2211 op_PFDRL uint32 = 0xC602
2212 op_PFMF uint32 = 0xB9AF
2213 op_PFPO uint32 = 0x010A
2214 op_PGIN uint32 = 0xB22E
2215 op_PGOUT uint32 = 0xB22F
2216 op_PKA uint32 = 0xE900
2217 op_PKU uint32 = 0xE100
2218 op_PLO uint32 = 0xEE00
2219 op_POPCNT uint32 = 0xB9E1
2220 op_PPA uint32 = 0xB2E8
2221 op_PR uint32 = 0x0101
2222 op_PT uint32 = 0xB228
2223 op_PTF uint32 = 0xB9A2
2224 op_PTFF uint32 = 0x0104
2225 op_PTI uint32 = 0xB99E
2226 op_PTLB uint32 = 0xB20D
2227 op_QADTR uint32 = 0xB3F5
2228 op_QAXTR uint32 = 0xB3FD
2229 op_RCHP uint32 = 0xB23B
2230 op_RISBG uint32 = 0xEC55
2231 op_RISBGN uint32 = 0xEC59
2232 op_RISBHG uint32 = 0xEC5D
2233 op_RISBLG uint32 = 0xEC51
2234 op_RLL uint32 = 0xEB1D
2235 op_RLLG uint32 = 0xEB1C
2236 op_RNSBG uint32 = 0xEC54
2237 op_ROSBG uint32 = 0xEC56
2238 op_RP uint32 = 0xB277
2239 op_RRBE uint32 = 0xB22A
2240 op_RRBM uint32 = 0xB9AE
2241 op_RRDTR uint32 = 0xB3F7
2242 op_RRXTR uint32 = 0xB3FF
2243 op_RSCH uint32 = 0xB238
2244 op_RXSBG uint32 = 0xEC57
2245 op_S uint32 = 0x5B00
2246 op_SAC uint32 = 0xB219
2247 op_SACF uint32 = 0xB279
2248 op_SAL uint32 = 0xB237
2249 op_SAM24 uint32 = 0x010C
2250 op_SAM31 uint32 = 0x010D
2251 op_SAM64 uint32 = 0x010E
2252 op_SAR uint32 = 0xB24E
2253 op_SCHM uint32 = 0xB23C
2254 op_SCK uint32 = 0xB204
2255 op_SCKC uint32 = 0xB206
2256 op_SCKPF uint32 = 0x0107
2257 op_SD uint32 = 0x6B00
2258 op_SDB uint32 = 0xED1B
2259 op_SDBR uint32 = 0xB31B
2260 op_SDR uint32 = 0x2B00
2261 op_SDTR uint32 = 0xB3D3
2262 op_SDTRA uint32 = 0xB3D3
2263 op_SE uint32 = 0x7B00
2264 op_SEB uint32 = 0xED0B
2265 op_SEBR uint32 = 0xB30B
2266 op_SER uint32 = 0x3B00
2267 op_SFASR uint32 = 0xB385
2268 op_SFPC uint32 = 0xB384
2269 op_SG uint32 = 0xE309
2270 op_SGF uint32 = 0xE319
2271 op_SGFR uint32 = 0xB919
2272 op_SGR uint32 = 0xB909
2273 op_SGRK uint32 = 0xB9E9
2274 op_SH uint32 = 0x4B00
2275 op_SHHHR uint32 = 0xB9C9
2276 op_SHHLR uint32 = 0xB9D9
2277 op_SHY uint32 = 0xE37B
2278 op_SIGP uint32 = 0xAE00
2279 op_SL uint32 = 0x5F00
2280 op_SLA uint32 = 0x8B00
2281 op_SLAG uint32 = 0xEB0B
2282 op_SLAK uint32 = 0xEBDD
2283 op_SLB uint32 = 0xE399
2284 op_SLBG uint32 = 0xE389
2285 op_SLBGR uint32 = 0xB989
2286 op_SLBR uint32 = 0xB999
2287 op_SLDA uint32 = 0x8F00
2288 op_SLDL uint32 = 0x8D00
2289 op_SLDT uint32 = 0xED40
2290 op_SLFI uint32 = 0xC205
2291 op_SLG uint32 = 0xE30B
2292 op_SLGF uint32 = 0xE31B
2293 op_SLGFI uint32 = 0xC204
2294 op_SLGFR uint32 = 0xB91B
2295 op_SLGR uint32 = 0xB90B
2296 op_SLGRK uint32 = 0xB9EB
2297 op_SLHHHR uint32 = 0xB9CB
2298 op_SLHHLR uint32 = 0xB9DB
2299 op_SLL uint32 = 0x8900
2300 op_SLLG uint32 = 0xEB0D
2301 op_SLLK uint32 = 0xEBDF
2302 op_SLR uint32 = 0x1F00
2303 op_SLRK uint32 = 0xB9FB
2304 op_SLXT uint32 = 0xED48
2305 op_SLY uint32 = 0xE35F
2306 op_SP uint32 = 0xFB00
2307 op_SPKA uint32 = 0xB20A
2308 op_SPM uint32 = 0x0400
2309 op_SPT uint32 = 0xB208
2310 op_SPX uint32 = 0xB210
2311 op_SQD uint32 = 0xED35
2312 op_SQDB uint32 = 0xED15
2313 op_SQDBR uint32 = 0xB315
2314 op_SQDR uint32 = 0xB244
2315 op_SQE uint32 = 0xED34
2316 op_SQEB uint32 = 0xED14
2317 op_SQEBR uint32 = 0xB314
2318 op_SQER uint32 = 0xB245
2319 op_SQXBR uint32 = 0xB316
2320 op_SQXR uint32 = 0xB336
2321 op_SR uint32 = 0x1B00
2322 op_SRA uint32 = 0x8A00
2323 op_SRAG uint32 = 0xEB0A
2324 op_SRAK uint32 = 0xEBDC
2325 op_SRDA uint32 = 0x8E00
2326 op_SRDL uint32 = 0x8C00
2327 op_SRDT uint32 = 0xED41
2328 op_SRK uint32 = 0xB9F9
2329 op_SRL uint32 = 0x8800
2330 op_SRLG uint32 = 0xEB0C
2331 op_SRLK uint32 = 0xEBDE
2332 op_SRNM uint32 = 0xB299
2333 op_SRNMB uint32 = 0xB2B8
2334 op_SRNMT uint32 = 0xB2B9
2335 op_SRP uint32 = 0xF000
2336 op_SRST uint32 = 0xB25E
2337 op_SRSTU uint32 = 0xB9BE
2338 op_SRXT uint32 = 0xED49
2339 op_SSAIR uint32 = 0xB99F
2340 op_SSAR uint32 = 0xB225
2341 op_SSCH uint32 = 0xB233
2342 op_SSKE uint32 = 0xB22B
2343 op_SSM uint32 = 0x8000
2344 op_ST uint32 = 0x5000
2345 op_STAM uint32 = 0x9B00
2346 op_STAMY uint32 = 0xEB9B
2347 op_STAP uint32 = 0xB212
2348 op_STC uint32 = 0x4200
2349 op_STCH uint32 = 0xE3C3
2350 op_STCK uint32 = 0xB205
2351 op_STCKC uint32 = 0xB207
2352 op_STCKE uint32 = 0xB278
2353 op_STCKF uint32 = 0xB27C
2354 op_STCM uint32 = 0xBE00
2355 op_STCMH uint32 = 0xEB2C
2356 op_STCMY uint32 = 0xEB2D
2357 op_STCPS uint32 = 0xB23A
2358 op_STCRW uint32 = 0xB239
2359 op_STCTG uint32 = 0xEB25
2360 op_STCTL uint32 = 0xB600
2361 op_STCY uint32 = 0xE372
2362 op_STD uint32 = 0x6000
2363 op_STDY uint32 = 0xED67
2364 op_STE uint32 = 0x7000
2365 op_STEY uint32 = 0xED66
2366 op_STFH uint32 = 0xE3CB
2367 op_STFL uint32 = 0xB2B1
2368 op_STFLE uint32 = 0xB2B0
2369 op_STFPC uint32 = 0xB29C
2370 op_STG uint32 = 0xE324
2371 op_STGRL uint32 = 0xC40B
2372 op_STH uint32 = 0x4000
2373 op_STHH uint32 = 0xE3C7
2374 op_STHRL uint32 = 0xC407
2375 op_STHY uint32 = 0xE370
2376 op_STIDP uint32 = 0xB202
2377 op_STM uint32 = 0x9000
2378 op_STMG uint32 = 0xEB24
2379 op_STMH uint32 = 0xEB26
2380 op_STMY uint32 = 0xEB90
2381 op_STNSM uint32 = 0xAC00
2382 op_STOC uint32 = 0xEBF3
2383 op_STOCG uint32 = 0xEBE3
2384 op_STOSM uint32 = 0xAD00
2385 op_STPQ uint32 = 0xE38E
2386 op_STPT uint32 = 0xB209
2387 op_STPX uint32 = 0xB211
2388 op_STRAG uint32 = 0xE502
2389 op_STRL uint32 = 0xC40F
2390 op_STRV uint32 = 0xE33E
2391 op_STRVG uint32 = 0xE32F
2392 op_STRVH uint32 = 0xE33F
2393 op_STSCH uint32 = 0xB234
2394 op_STSI uint32 = 0xB27D
2395 op_STURA uint32 = 0xB246
2396 op_STURG uint32 = 0xB925
2397 op_STY uint32 = 0xE350
2398 op_SU uint32 = 0x7F00
2399 op_SUR uint32 = 0x3F00
2400 op_SVC uint32 = 0x0A00
2401 op_SW uint32 = 0x6F00
2402 op_SWR uint32 = 0x2F00
2403 op_SXBR uint32 = 0xB34B
2404 op_SXR uint32 = 0x3700
2405 op_SXTR uint32 = 0xB3DB
2406 op_SXTRA uint32 = 0xB3DB
2407 op_SY uint32 = 0xE35B
2408 op_TABORT uint32 = 0xB2FC
2409 op_TAM uint32 = 0x010B
2410 op_TAR uint32 = 0xB24C
2411 op_TB uint32 = 0xB22C
2412 op_TBDR uint32 = 0xB351
2413 op_TBEDR uint32 = 0xB350
2414 op_TBEGIN uint32 = 0xE560
2415 op_TBEGINC uint32 = 0xE561
2416 op_TCDB uint32 = 0xED11
2417 op_TCEB uint32 = 0xED10
2418 op_TCXB uint32 = 0xED12
2419 op_TDCDT uint32 = 0xED54
2420 op_TDCET uint32 = 0xED50
2421 op_TDCXT uint32 = 0xED58
2422 op_TDGDT uint32 = 0xED55
2423 op_TDGET uint32 = 0xED51
2424 op_TDGXT uint32 = 0xED59
2425 op_TEND uint32 = 0xB2F8
2426 op_THDER uint32 = 0xB358
2427 op_THDR uint32 = 0xB359
2428 op_TM uint32 = 0x9100
2429 op_TMH uint32 = 0xA700
2430 op_TMHH uint32 = 0xA702
2431 op_TMHL uint32 = 0xA703
2432 op_TML uint32 = 0xA701
2433 op_TMLH uint32 = 0xA700
2434 op_TMLL uint32 = 0xA701
2435 op_TMY uint32 = 0xEB51
2436 op_TP uint32 = 0xEBC0
2437 op_TPI uint32 = 0xB236
2438 op_TPROT uint32 = 0xE501
2439 op_TR uint32 = 0xDC00
2440 op_TRACE uint32 = 0x9900
2441 op_TRACG uint32 = 0xEB0F
2442 op_TRAP2 uint32 = 0x01FF
2443 op_TRAP4 uint32 = 0xB2FF
2444 op_TRE uint32 = 0xB2A5
2445 op_TROO uint32 = 0xB993
2446 op_TROT uint32 = 0xB992
2447 op_TRT uint32 = 0xDD00
2448 op_TRTE uint32 = 0xB9BF
2449 op_TRTO uint32 = 0xB991
2450 op_TRTR uint32 = 0xD000
2451 op_TRTRE uint32 = 0xB9BD
2452 op_TRTT uint32 = 0xB990
2453 op_TS uint32 = 0x9300
2454 op_TSCH uint32 = 0xB235
2455 op_UNPK uint32 = 0xF300
2456 op_UNPKA uint32 = 0xEA00
2457 op_UNPKU uint32 = 0xE200
2458 op_UPT uint32 = 0x0102
2459 op_X uint32 = 0x5700
2460 op_XC uint32 = 0xD700
2461 op_XG uint32 = 0xE382
2462 op_XGR uint32 = 0xB982
2463 op_XGRK uint32 = 0xB9E7
2464 op_XI uint32 = 0x9700
2465 op_XIHF uint32 = 0xC006
2466 op_XILF uint32 = 0xC007
2467 op_XIY uint32 = 0xEB57
2468 op_XR uint32 = 0x1700
2469 op_XRK uint32 = 0xB9F7
2470 op_XSCH uint32 = 0xB276
2471 op_XY uint32 = 0xE357
2472 op_ZAP uint32 = 0xF800
2473
2474
2475 op_CXPT uint32 = 0xEDAF
2476 op_CDPT uint32 = 0xEDAE
2477 op_CPXT uint32 = 0xEDAD
2478 op_CPDT uint32 = 0xEDAC
2479 op_LZRF uint32 = 0xE33B
2480 op_LZRG uint32 = 0xE32A
2481 op_LCCB uint32 = 0xE727
2482 op_LOCHHI uint32 = 0xEC4E
2483 op_LOCHI uint32 = 0xEC42
2484 op_LOCGHI uint32 = 0xEC46
2485 op_LOCFH uint32 = 0xEBE0
2486 op_LOCFHR uint32 = 0xB9E0
2487 op_LLZRGF uint32 = 0xE33A
2488 op_STOCFH uint32 = 0xEBE1
2489 op_VA uint32 = 0xE7F3
2490 op_VACC uint32 = 0xE7F1
2491 op_VAC uint32 = 0xE7BB
2492 op_VACCC uint32 = 0xE7B9
2493 op_VN uint32 = 0xE768
2494 op_VNC uint32 = 0xE769
2495 op_VAVG uint32 = 0xE7F2
2496 op_VAVGL uint32 = 0xE7F0
2497 op_VCKSM uint32 = 0xE766
2498 op_VCEQ uint32 = 0xE7F8
2499 op_VCH uint32 = 0xE7FB
2500 op_VCHL uint32 = 0xE7F9
2501 op_VCLZ uint32 = 0xE753
2502 op_VCTZ uint32 = 0xE752
2503 op_VEC uint32 = 0xE7DB
2504 op_VECL uint32 = 0xE7D9
2505 op_VERIM uint32 = 0xE772
2506 op_VERLL uint32 = 0xE733
2507 op_VERLLV uint32 = 0xE773
2508 op_VESLV uint32 = 0xE770
2509 op_VESL uint32 = 0xE730
2510 op_VESRA uint32 = 0xE73A
2511 op_VESRAV uint32 = 0xE77A
2512 op_VESRL uint32 = 0xE738
2513 op_VESRLV uint32 = 0xE778
2514 op_VX uint32 = 0xE76D
2515 op_VFAE uint32 = 0xE782
2516 op_VFEE uint32 = 0xE780
2517 op_VFENE uint32 = 0xE781
2518 op_VFA uint32 = 0xE7E3
2519 op_WFK uint32 = 0xE7CA
2520 op_VFCE uint32 = 0xE7E8
2521 op_VFCH uint32 = 0xE7EB
2522 op_VFCHE uint32 = 0xE7EA
2523 op_WFC uint32 = 0xE7CB
2524 op_VCDG uint32 = 0xE7C3
2525 op_VCDLG uint32 = 0xE7C1
2526 op_VCGD uint32 = 0xE7C2
2527 op_VCLGD uint32 = 0xE7C0
2528 op_VFD uint32 = 0xE7E5
2529 op_VLDE uint32 = 0xE7C4
2530 op_VLED uint32 = 0xE7C5
2531 op_VFM uint32 = 0xE7E7
2532 op_VFMA uint32 = 0xE78F
2533 op_VFMS uint32 = 0xE78E
2534 op_VFPSO uint32 = 0xE7CC
2535 op_VFSQ uint32 = 0xE7CE
2536 op_VFS uint32 = 0xE7E2
2537 op_VFTCI uint32 = 0xE74A
2538 op_VGFM uint32 = 0xE7B4
2539 op_VGFMA uint32 = 0xE7BC
2540 op_VGEF uint32 = 0xE713
2541 op_VGEG uint32 = 0xE712
2542 op_VGBM uint32 = 0xE744
2543 op_VGM uint32 = 0xE746
2544 op_VISTR uint32 = 0xE75C
2545 op_VL uint32 = 0xE706
2546 op_VLR uint32 = 0xE756
2547 op_VLREP uint32 = 0xE705
2548 op_VLC uint32 = 0xE7DE
2549 op_VLEH uint32 = 0xE701
2550 op_VLEF uint32 = 0xE703
2551 op_VLEG uint32 = 0xE702
2552 op_VLEB uint32 = 0xE700
2553 op_VLEIH uint32 = 0xE741
2554 op_VLEIF uint32 = 0xE743
2555 op_VLEIG uint32 = 0xE742
2556 op_VLEIB uint32 = 0xE740
2557 op_VFI uint32 = 0xE7C7
2558 op_VLGV uint32 = 0xE721
2559 op_VLLEZ uint32 = 0xE704
2560 op_VLM uint32 = 0xE736
2561 op_VLP uint32 = 0xE7DF
2562 op_VLBB uint32 = 0xE707
2563 op_VLVG uint32 = 0xE722
2564 op_VLVGP uint32 = 0xE762
2565 op_VLL uint32 = 0xE737
2566 op_VMX uint32 = 0xE7FF
2567 op_VMXL uint32 = 0xE7FD
2568 op_VMRH uint32 = 0xE761
2569 op_VMRL uint32 = 0xE760
2570 op_VMN uint32 = 0xE7FE
2571 op_VMNL uint32 = 0xE7FC
2572 op_VMAE uint32 = 0xE7AE
2573 op_VMAH uint32 = 0xE7AB
2574 op_VMALE uint32 = 0xE7AC
2575 op_VMALH uint32 = 0xE7A9
2576 op_VMALO uint32 = 0xE7AD
2577 op_VMAL uint32 = 0xE7AA
2578 op_VMAO uint32 = 0xE7AF
2579 op_VME uint32 = 0xE7A6
2580 op_VMH uint32 = 0xE7A3
2581 op_VMLE uint32 = 0xE7A4
2582 op_VMLH uint32 = 0xE7A1
2583 op_VMLO uint32 = 0xE7A5
2584 op_VML uint32 = 0xE7A2
2585 op_VMO uint32 = 0xE7A7
2586 op_VNO uint32 = 0xE76B
2587 op_VO uint32 = 0xE76A
2588 op_VPK uint32 = 0xE794
2589 op_VPKLS uint32 = 0xE795
2590 op_VPKS uint32 = 0xE797
2591 op_VPERM uint32 = 0xE78C
2592 op_VPDI uint32 = 0xE784
2593 op_VPOPCT uint32 = 0xE750
2594 op_VREP uint32 = 0xE74D
2595 op_VREPI uint32 = 0xE745
2596 op_VSCEF uint32 = 0xE71B
2597 op_VSCEG uint32 = 0xE71A
2598 op_VSEL uint32 = 0xE78D
2599 op_VSL uint32 = 0xE774
2600 op_VSLB uint32 = 0xE775
2601 op_VSLDB uint32 = 0xE777
2602 op_VSRA uint32 = 0xE77E
2603 op_VSRAB uint32 = 0xE77F
2604 op_VSRL uint32 = 0xE77C
2605 op_VSRLB uint32 = 0xE77D
2606 op_VSEG uint32 = 0xE75F
2607 op_VST uint32 = 0xE70E
2608 op_VSTEH uint32 = 0xE709
2609 op_VSTEF uint32 = 0xE70B
2610 op_VSTEG uint32 = 0xE70A
2611 op_VSTEB uint32 = 0xE708
2612 op_VSTM uint32 = 0xE73E
2613 op_VSTL uint32 = 0xE73F
2614 op_VSTRC uint32 = 0xE78A
2615 op_VS uint32 = 0xE7F7
2616 op_VSCBI uint32 = 0xE7F5
2617 op_VSBCBI uint32 = 0xE7BD
2618 op_VSBI uint32 = 0xE7BF
2619 op_VSUMG uint32 = 0xE765
2620 op_VSUMQ uint32 = 0xE767
2621 op_VSUM uint32 = 0xE764
2622 op_VTM uint32 = 0xE7D8
2623 op_VUPH uint32 = 0xE7D7
2624 op_VUPLH uint32 = 0xE7D5
2625 op_VUPLL uint32 = 0xE7D4
2626 op_VUPL uint32 = 0xE7D6
2627 op_VMSL uint32 = 0xE7B8
2628 )
2629
2630 func oclass(a *obj.Addr) int {
2631 return int(a.Class) - 1
2632 }
2633
2634
2635
2636 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc {
2637 if sym == nil {
2638 c.ctxt.Diag("require symbol to apply relocation")
2639 }
2640 offset := int64(2)
2641 rel := obj.Addrel(c.cursym)
2642 rel.Off = int32(c.pc + offset)
2643 rel.Siz = 4
2644 rel.Sym = sym
2645 rel.Add = add + offset + int64(rel.Siz)
2646 rel.Type = objabi.R_PCRELDBL
2647 return rel
2648 }
2649
2650 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc {
2651 if sym == nil {
2652 c.ctxt.Diag("require symbol to apply relocation")
2653 }
2654 offset += int64(2)
2655 rel := obj.Addrel(c.cursym)
2656 rel.Off = int32(c.pc + offset)
2657 rel.Siz = 4
2658 rel.Sym = sym
2659 rel.Add = add + offset + int64(rel.Siz)
2660 rel.Type = objabi.R_PCRELDBL
2661 return rel
2662 }
2663
2664
2665
2666 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc {
2667 if sym == nil {
2668 c.ctxt.Diag("require symbol to apply relocation")
2669 }
2670 offset := int64(2)
2671 rel := obj.Addrel(c.cursym)
2672 rel.Off = int32(c.pc + offset)
2673 rel.Siz = 4
2674 rel.Sym = sym
2675 rel.Add = add + offset + int64(rel.Siz)
2676 rel.Type = objabi.R_CALL
2677 return rel
2678 }
2679
2680 func (c *ctxtz) branchMask(p *obj.Prog) CCMask {
2681 switch p.As {
2682 case ABRC, ALOCR, ALOCGR,
2683 ACRJ, ACGRJ, ACIJ, ACGIJ,
2684 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ:
2685 return CCMask(p.From.Offset)
2686 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
2687 return Equal
2688 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
2689 return GreaterOrEqual
2690 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
2691 return Greater
2692 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
2693 return LessOrEqual
2694 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
2695 return Less
2696 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
2697 return NotEqual
2698 case ABLEU:
2699 return NotGreater
2700 case ABLTU:
2701 return LessOrUnordered
2702 case ABVC:
2703 return Never
2704 case ABVS:
2705 return Unordered
2706 }
2707 c.ctxt.Diag("unknown conditional branch %v", p.As)
2708 return Always
2709 }
2710
2711 func regtmp(p *obj.Prog) uint32 {
2712 p.Mark |= USETMP
2713 return REGTMP
2714 }
2715
2716 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
2717 o := c.oplook(p)
2718
2719 if o == nil {
2720 return
2721 }
2722
2723
2724
2725
2726 switch o.i {
2727 default:
2728 c.ctxt.Diag("unknown index %d", o.i)
2729
2730 case 0:
2731 break
2732
2733 case 1:
2734 switch p.As {
2735 default:
2736 c.ctxt.Diag("unhandled operation: %v", p.As)
2737 case AMOVD:
2738 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2739
2740 case AMOVW:
2741 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2742 case AMOVH:
2743 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2744 case AMOVB:
2745 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2746
2747 case AMOVWZ:
2748 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2749 case AMOVHZ:
2750 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2751 case AMOVBZ:
2752 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2753
2754 case AMOVDBR:
2755 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2756 case AMOVWBR:
2757 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2758
2759 case AFMOVD, AFMOVS:
2760 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2761 }
2762
2763 case 2:
2764 r := p.Reg
2765 if r == 0 {
2766 r = p.To.Reg
2767 }
2768
2769 var opcode uint32
2770
2771 switch p.As {
2772 default:
2773 c.ctxt.Diag("invalid opcode")
2774 case AADD:
2775 opcode = op_AGRK
2776 case AADDC:
2777 opcode = op_ALGRK
2778 case AADDE:
2779 opcode = op_ALCGR
2780 case AADDW:
2781 opcode = op_ARK
2782 case AMULLW:
2783 opcode = op_MSGFR
2784 case AMULLD:
2785 opcode = op_MSGR
2786 case ADIVW, AMODW:
2787 opcode = op_DSGFR
2788 case ADIVWU, AMODWU:
2789 opcode = op_DLR
2790 case ADIVD, AMODD:
2791 opcode = op_DSGR
2792 case ADIVDU, AMODDU:
2793 opcode = op_DLGR
2794 }
2795
2796 switch p.As {
2797 default:
2798
2799 case AADD, AADDC, AADDW:
2800 if p.As == AADDW && r == p.To.Reg {
2801 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2802 } else {
2803 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2804 }
2805
2806 case AADDE, AMULLW, AMULLD:
2807 if r == p.To.Reg {
2808 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2809 } else if p.From.Reg == p.To.Reg {
2810 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2811 } else {
2812 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2813 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2814 }
2815
2816 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2817 if p.As == ADIVWU || p.As == ADIVDU {
2818 zRI(op_LGHI, regtmp(p), 0, asm)
2819 }
2820 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2821 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2822 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2823
2824 case AMODW, AMODWU, AMODD, AMODDU:
2825 if p.As == AMODWU || p.As == AMODDU {
2826 zRI(op_LGHI, regtmp(p), 0, asm)
2827 }
2828 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2829 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2830 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2831
2832 }
2833
2834 case 3:
2835 v := c.vregoff(&p.From)
2836 switch p.As {
2837 case AMOVBZ:
2838 v = int64(uint8(v))
2839 case AMOVHZ:
2840 v = int64(uint16(v))
2841 case AMOVWZ:
2842 v = int64(uint32(v))
2843 case AMOVB:
2844 v = int64(int8(v))
2845 case AMOVH:
2846 v = int64(int16(v))
2847 case AMOVW:
2848 v = int64(int32(v))
2849 }
2850 if int64(int16(v)) == v {
2851 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2852 } else if v&0xffff0000 == v {
2853 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2854 } else if v&0xffff00000000 == v {
2855 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2856 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2857 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2858 } else if int64(int32(v)) == v {
2859 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2860 } else if int64(uint32(v)) == v {
2861 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2862 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2863 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2864 } else {
2865 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2866 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2867 }
2868
2869 case 4:
2870 r := p.Reg
2871 if r == 0 {
2872 r = p.To.Reg
2873 }
2874 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2875 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm)
2876 switch p.As {
2877 case AMULHDU:
2878
2879 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2880 case AMULHD:
2881
2882
2883 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2884 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2885 zRRE(op_SGR, regtmp(p), REGTMP2, asm)
2886 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2887 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2888 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm)
2889 }
2890
2891 case 5:
2892 zI(op_SVC, 0, asm)
2893
2894 case 6:
2895 var oprr, oprre, oprrf uint32
2896 switch p.As {
2897 case AAND:
2898 oprre = op_NGR
2899 oprrf = op_NGRK
2900 case AANDW:
2901 oprr = op_NR
2902 oprrf = op_NRK
2903 case AOR:
2904 oprre = op_OGR
2905 oprrf = op_OGRK
2906 case AORW:
2907 oprr = op_OR
2908 oprrf = op_ORK
2909 case AXOR:
2910 oprre = op_XGR
2911 oprrf = op_XGRK
2912 case AXORW:
2913 oprr = op_XR
2914 oprrf = op_XRK
2915 }
2916 if p.Reg == 0 {
2917 if oprr != 0 {
2918 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2919 } else {
2920 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2921 }
2922 } else {
2923 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2924 }
2925
2926 case 7:
2927 d2 := c.vregoff(&p.From)
2928 b2 := p.From.Reg
2929 r3 := p.Reg
2930 if r3 == 0 {
2931 r3 = p.To.Reg
2932 }
2933 r1 := p.To.Reg
2934 var opcode uint32
2935 switch p.As {
2936 default:
2937 case ASLD:
2938 opcode = op_SLLG
2939 case ASRD:
2940 opcode = op_SRLG
2941 case ASLW:
2942 opcode = op_SLLK
2943 case ASRW:
2944 opcode = op_SRLK
2945 case ARLL:
2946 opcode = op_RLL
2947 case ARLLG:
2948 opcode = op_RLLG
2949 case ASRAW:
2950 opcode = op_SRAK
2951 case ASRAD:
2952 opcode = op_SRAG
2953 }
2954 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2955
2956 case 8:
2957 if p.To.Reg&1 != 0 {
2958 c.ctxt.Diag("target must be an even-numbered register")
2959 }
2960
2961 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2962
2963 case 9:
2964 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2965
2966 case 10:
2967 r := int(p.Reg)
2968
2969 switch p.As {
2970 default:
2971 case ASUB:
2972 if r == 0 {
2973 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2974 } else {
2975 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2976 }
2977 case ASUBC:
2978 if r == 0 {
2979 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2980 } else {
2981 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2982 }
2983 case ASUBE:
2984 if r == 0 {
2985 r = int(p.To.Reg)
2986 }
2987 if r == int(p.To.Reg) {
2988 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2989 } else if p.From.Reg == p.To.Reg {
2990 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm)
2991 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2992 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm)
2993 } else {
2994 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2995 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2996 }
2997 case ASUBW:
2998 if r == 0 {
2999 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3000 } else {
3001 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
3002 }
3003 }
3004
3005 case 11:
3006 v := int32(0)
3007
3008 if p.To.Target() != nil {
3009 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3010 }
3011
3012 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
3013 zRI(op_BRC, 0xF, uint32(v), asm)
3014 } else {
3015 if p.As == ABL {
3016 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
3017 } else {
3018 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
3019 }
3020 if p.To.Sym != nil {
3021 c.addcallreloc(p.To.Sym, p.To.Offset)
3022 }
3023 }
3024
3025 case 12:
3026 r1 := p.To.Reg
3027 d2 := c.vregoff(&p.From)
3028 b2 := p.From.Reg
3029 if b2 == 0 {
3030 b2 = REGSP
3031 }
3032 x2 := p.From.Index
3033 if -DISP20/2 > d2 || d2 >= DISP20/2 {
3034 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3035 if x2 != 0 {
3036 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3037 }
3038 x2 = int16(regtmp(p))
3039 d2 = 0
3040 }
3041 var opx, opxy uint32
3042 switch p.As {
3043 case AADD:
3044 opxy = op_AG
3045 case AADDC:
3046 opxy = op_ALG
3047 case AADDE:
3048 opxy = op_ALCG
3049 case AADDW:
3050 opx = op_A
3051 opxy = op_AY
3052 case AMULLW:
3053 opx = op_MS
3054 opxy = op_MSY
3055 case AMULLD:
3056 opxy = op_MSG
3057 case ASUB:
3058 opxy = op_SG
3059 case ASUBC:
3060 opxy = op_SLG
3061 case ASUBE:
3062 opxy = op_SLBG
3063 case ASUBW:
3064 opx = op_S
3065 opxy = op_SY
3066 case AAND:
3067 opxy = op_NG
3068 case AANDW:
3069 opx = op_N
3070 opxy = op_NY
3071 case AOR:
3072 opxy = op_OG
3073 case AORW:
3074 opx = op_O
3075 opxy = op_OY
3076 case AXOR:
3077 opxy = op_XG
3078 case AXORW:
3079 opx = op_X
3080 opxy = op_XY
3081 }
3082 if opx != 0 && 0 <= d2 && d2 < DISP12 {
3083 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3084 } else {
3085 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3086 }
3087
3088 case 13:
3089 r1 := p.To.Reg
3090 r2 := p.RestArgs[2].Reg
3091 i3 := uint8(p.From.Offset)
3092 i4 := uint8(p.RestArgs[0].Offset)
3093 i5 := uint8(p.RestArgs[1].Offset)
3094 switch p.As {
3095 case ARNSBGT, ARXSBGT, AROSBGT:
3096 i3 |= 0x80
3097 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ:
3098 i4 |= 0x80
3099 }
3100 var opcode uint32
3101 switch p.As {
3102 case ARNSBG, ARNSBGT:
3103 opcode = op_RNSBG
3104 case ARXSBG, ARXSBGT:
3105 opcode = op_RXSBG
3106 case AROSBG, AROSBGT:
3107 opcode = op_ROSBG
3108 case ARISBG, ARISBGZ:
3109 opcode = op_RISBG
3110 case ARISBGN, ARISBGNZ:
3111 opcode = op_RISBGN
3112 case ARISBHG, ARISBHGZ:
3113 opcode = op_RISBHG
3114 case ARISBLG, ARISBLGZ:
3115 opcode = op_RISBLG
3116 }
3117 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm)
3118
3119 case 15:
3120 r := p.To.Reg
3121 if p.As == ABCL || p.As == ABL {
3122 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
3123 } else {
3124 zRR(op_BCR, uint32(Always), uint32(r), asm)
3125 }
3126
3127 case 16:
3128 v := int32(0)
3129 if p.To.Target() != nil {
3130 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3131 }
3132 mask := uint32(c.branchMask(p))
3133 if p.To.Sym == nil && int32(int16(v)) == v {
3134 zRI(op_BRC, mask, uint32(v), asm)
3135 } else {
3136 zRIL(_c, op_BRCL, mask, uint32(v), asm)
3137 }
3138 if p.To.Sym != nil {
3139 c.addrilreloc(p.To.Sym, p.To.Offset)
3140 }
3141
3142 case 17:
3143 m3 := uint32(c.branchMask(p))
3144 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3145
3146 case 18:
3147 if p.As == ABL {
3148 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
3149 } else {
3150 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm)
3151 }
3152
3153 case 19:
3154 d := c.vregoff(&p.From)
3155 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
3156 if d&1 != 0 {
3157 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
3158 d -= 1
3159 }
3160 c.addrilreloc(p.From.Sym, d)
3161
3162 case 21:
3163 v := c.vregoff(&p.From)
3164 r := p.Reg
3165 if r == 0 {
3166 r = p.To.Reg
3167 }
3168 switch p.As {
3169 case ASUB:
3170 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm)
3171 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm)
3172 case ASUBC:
3173 if r != p.To.Reg {
3174 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3175 }
3176 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
3177 case ASUBW:
3178 if r != p.To.Reg {
3179 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3180 }
3181 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
3182 }
3183
3184 case 22:
3185 v := c.vregoff(&p.From)
3186 r := p.Reg
3187 if r == 0 {
3188 r = p.To.Reg
3189 }
3190 var opri, opril, oprie uint32
3191 switch p.As {
3192 case AADD:
3193 opri = op_AGHI
3194 opril = op_AGFI
3195 oprie = op_AGHIK
3196 case AADDC:
3197 opril = op_ALGFI
3198 oprie = op_ALGHSIK
3199 case AADDW:
3200 opri = op_AHI
3201 opril = op_AFI
3202 oprie = op_AHIK
3203 case AMULLW:
3204 opri = op_MHI
3205 opril = op_MSFI
3206 case AMULLD:
3207 opri = op_MGHI
3208 opril = op_MSGFI
3209 }
3210 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) {
3211 switch p.As {
3212 case AADD, AADDC, AMULLD:
3213 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3214 case AADDW, AMULLW:
3215 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3216 }
3217 r = p.To.Reg
3218 }
3219 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v {
3220 zRI(opri, uint32(p.To.Reg), uint32(v), asm)
3221 } else if oprie != 0 && int64(int16(v)) == v {
3222 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
3223 } else {
3224 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm)
3225 }
3226
3227 case 23:
3228
3229 v := c.vregoff(&p.From)
3230 switch p.As {
3231 default:
3232 c.ctxt.Diag("%v is not supported", p)
3233 case AAND:
3234 if v >= 0 {
3235 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3236 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm)
3237 } else if int64(int16(v)) == v {
3238 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3239 } else {
3240 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3241 }
3242 case AOR:
3243 if int64(uint32(v)) != v {
3244 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3245 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm)
3246 } else if int64(uint16(v)) == v {
3247 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3248 } else {
3249 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3250 }
3251 case AXOR:
3252 if int64(uint32(v)) != v {
3253 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3254 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm)
3255 } else {
3256 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3257 }
3258 }
3259
3260 case 24:
3261 v := c.vregoff(&p.From)
3262 switch p.As {
3263 case AANDW:
3264 if uint32(v&0xffff0000) == 0xffff0000 {
3265 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3266 } else if uint32(v&0x0000ffff) == 0x0000ffff {
3267 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3268 } else {
3269 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3270 }
3271 case AORW:
3272 if uint32(v&0xffff0000) == 0 {
3273 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3274 } else if uint32(v&0x0000ffff) == 0 {
3275 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3276 } else {
3277 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3278 }
3279 case AXORW:
3280 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3281 }
3282
3283 case 25:
3284 m3 := uint32(c.branchMask(p))
3285 var opcode uint32
3286 switch p.As {
3287 case ALOCR:
3288 opcode = op_LOCR
3289 case ALOCGR:
3290 opcode = op_LOCGR
3291 }
3292 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3293
3294 case 26:
3295 v := c.regoff(&p.From)
3296 r := p.From.Reg
3297 if r == 0 {
3298 r = REGSP
3299 }
3300 i := p.From.Index
3301 if v >= 0 && v < DISP12 {
3302 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3303 } else if v >= -DISP20/2 && v < DISP20/2 {
3304 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3305 } else {
3306 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3307 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm)
3308 }
3309
3310 case 31:
3311 wd := uint64(c.vregoff(&p.From))
3312 *asm = append(*asm,
3313 uint8(wd>>56),
3314 uint8(wd>>48),
3315 uint8(wd>>40),
3316 uint8(wd>>32),
3317 uint8(wd>>24),
3318 uint8(wd>>16),
3319 uint8(wd>>8),
3320 uint8(wd))
3321
3322 case 32:
3323 var opcode uint32
3324 switch p.As {
3325 default:
3326 c.ctxt.Diag("invalid opcode")
3327 case AFADD:
3328 opcode = op_ADBR
3329 case AFADDS:
3330 opcode = op_AEBR
3331 case AFDIV:
3332 opcode = op_DDBR
3333 case AFDIVS:
3334 opcode = op_DEBR
3335 case AFMUL:
3336 opcode = op_MDBR
3337 case AFMULS:
3338 opcode = op_MEEBR
3339 case AFSUB:
3340 opcode = op_SDBR
3341 case AFSUBS:
3342 opcode = op_SEBR
3343 }
3344 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3345
3346 case 33:
3347 r := p.From.Reg
3348 if oclass(&p.From) == C_NONE {
3349 r = p.To.Reg
3350 }
3351 var opcode uint32
3352 switch p.As {
3353 default:
3354 case AFABS:
3355 opcode = op_LPDBR
3356 case AFNABS:
3357 opcode = op_LNDBR
3358 case ALPDFR:
3359 opcode = op_LPDFR
3360 case ALNDFR:
3361 opcode = op_LNDFR
3362 case AFNEG:
3363 opcode = op_LCDFR
3364 case AFNEGS:
3365 opcode = op_LCEBR
3366 case ALEDBR:
3367 opcode = op_LEDBR
3368 case ALDEBR:
3369 opcode = op_LDEBR
3370 case AFSQRT:
3371 opcode = op_SQDBR
3372 case AFSQRTS:
3373 opcode = op_SQEBR
3374 }
3375 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3376
3377 case 34:
3378 var opcode uint32
3379 switch p.As {
3380 default:
3381 c.ctxt.Diag("invalid opcode")
3382 case AFMADD:
3383 opcode = op_MADBR
3384 case AFMADDS:
3385 opcode = op_MAEBR
3386 case AFMSUB:
3387 opcode = op_MSDBR
3388 case AFMSUBS:
3389 opcode = op_MSEBR
3390 }
3391 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3392
3393 case 35:
3394 d2 := c.regoff(&p.To)
3395 b2 := p.To.Reg
3396 if b2 == 0 {
3397 b2 = REGSP
3398 }
3399 x2 := p.To.Index
3400 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3401 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3402 if x2 != 0 {
3403 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3404 }
3405 x2 = int16(regtmp(p))
3406 d2 = 0
3407 }
3408
3409 if op, ok := c.zopstore12(p.As); ok && isU12(d2) {
3410 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3411 } else {
3412 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3413 }
3414
3415 case 36:
3416 d2 := c.regoff(&p.From)
3417 b2 := p.From.Reg
3418 if b2 == 0 {
3419 b2 = REGSP
3420 }
3421 x2 := p.From.Index
3422 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3423 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3424 if x2 != 0 {
3425 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3426 }
3427 x2 = int16(regtmp(p))
3428 d2 = 0
3429 }
3430
3431 if op, ok := c.zopload12(p.As); ok && isU12(d2) {
3432 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3433 } else {
3434 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3435 }
3436
3437 case 40:
3438 wd := uint32(c.regoff(&p.From))
3439 if p.As == AWORD {
3440 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3441 } else {
3442 *asm = append(*asm, uint8(wd))
3443 }
3444
3445 case 41:
3446 r1 := p.From.Reg
3447 ri2 := (p.To.Target().Pc - p.Pc) >> 1
3448 if int64(int16(ri2)) != ri2 {
3449 c.ctxt.Diag("branch target too far away")
3450 }
3451 var opcode uint32
3452 switch p.As {
3453 case ABRCT:
3454 opcode = op_BRCT
3455 case ABRCTG:
3456 opcode = op_BRCTG
3457 }
3458 zRI(opcode, uint32(r1), uint32(ri2), asm)
3459
3460 case 47:
3461 r := p.From.Reg
3462 if r == 0 {
3463 r = p.To.Reg
3464 }
3465 switch p.As {
3466 case ANEG:
3467 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3468 case ANEGW:
3469 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
3470 }
3471
3472 case 48:
3473 m3 := c.vregoff(&p.From)
3474 if 0 > m3 || m3 > 7 {
3475 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3)
3476 }
3477 var opcode uint32
3478 switch p.As {
3479 case AFIEBR:
3480 opcode = op_FIEBR
3481 case AFIDBR:
3482 opcode = op_FIDBR
3483 }
3484 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3485
3486 case 49:
3487 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3488
3489 case 50:
3490 var opcode uint32
3491 switch p.As {
3492 case ALTEBR:
3493 opcode = op_LTEBR
3494 case ALTDBR:
3495 opcode = op_LTDBR
3496 }
3497 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3498
3499 case 51:
3500 var opcode uint32
3501 switch p.As {
3502 case ATCEB:
3503 opcode = op_TCEB
3504 case ATCDB:
3505 opcode = op_TCDB
3506 }
3507 d2 := c.regoff(&p.To)
3508 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm)
3509
3510 case 62:
3511 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3512
3513 case 66:
3514 zRR(op_BCR, uint32(Never), 0, asm)
3515
3516 case 67:
3517 var opcode uint32
3518 switch p.As {
3519 case AFMOVS:
3520 opcode = op_LZER
3521 case AFMOVD:
3522 opcode = op_LZDR
3523 }
3524 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3525
3526 case 68:
3527 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3528
3529 case 69:
3530 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3531
3532 case 70:
3533 if p.As == ACMPW || p.As == ACMPWU {
3534 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3535 } else {
3536 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3537 }
3538
3539 case 71:
3540 v := c.vregoff(&p.To)
3541 switch p.As {
3542 case ACMP, ACMPW:
3543 if int64(int32(v)) != v {
3544 c.ctxt.Diag("%v overflows an int32", v)
3545 }
3546 case ACMPU, ACMPWU:
3547 if int64(uint32(v)) != v {
3548 c.ctxt.Diag("%v overflows a uint32", v)
3549 }
3550 }
3551 if p.As == ACMP && int64(int16(v)) == v {
3552 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm)
3553 } else if p.As == ACMPW && int64(int16(v)) == v {
3554 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm)
3555 } else {
3556 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm)
3557 }
3558
3559 case 72:
3560 v := c.regoff(&p.From)
3561 d := c.regoff(&p.To)
3562 r := p.To.Reg
3563 if p.To.Index != 0 {
3564 c.ctxt.Diag("cannot use index register")
3565 }
3566 if r == 0 {
3567 r = REGSP
3568 }
3569 var opcode uint32
3570 switch p.As {
3571 case AMOVD:
3572 opcode = op_MVGHI
3573 case AMOVW, AMOVWZ:
3574 opcode = op_MVHI
3575 case AMOVH, AMOVHZ:
3576 opcode = op_MVHHI
3577 case AMOVB, AMOVBZ:
3578 opcode = op_MVI
3579 }
3580 if d < 0 || d >= DISP12 {
3581 if r == int16(regtmp(p)) {
3582 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r)
3583 }
3584 if d >= -DISP20/2 && d < DISP20/2 {
3585 if opcode == op_MVI {
3586 opcode = op_MVIY
3587 } else {
3588 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm)
3589 r = int16(regtmp(p))
3590 d = 0
3591 }
3592 } else {
3593 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm)
3594 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm)
3595 r = int16(regtmp(p))
3596 d = 0
3597 }
3598 }
3599 switch opcode {
3600 case op_MVI:
3601 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3602 case op_MVIY:
3603 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm)
3604 default:
3605 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3606 }
3607
3608 case 74:
3609 i2 := c.regoff(&p.To)
3610 switch p.As {
3611 case AMOVD:
3612 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3613 case AMOVW, AMOVWZ:
3614 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3615 case AMOVH, AMOVHZ:
3616 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3617 case AMOVB, AMOVBZ:
3618 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3619 adj := uint32(0)
3620 if i2&1 != 0 {
3621 i2 -= 1
3622 adj = 1
3623 }
3624 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm)
3625 case AFMOVD:
3626 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3627 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3628 case AFMOVS:
3629 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3630 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3631 }
3632 c.addrilreloc(p.To.Sym, int64(i2))
3633
3634 case 75:
3635 i2 := c.regoff(&p.From)
3636 switch p.As {
3637 case AMOVD:
3638 if i2&1 != 0 {
3639 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3640 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm)
3641 i2 -= 1
3642 } else {
3643 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3644 }
3645 case AMOVW:
3646 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3647 case AMOVWZ:
3648 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3649 case AMOVH:
3650 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3651 case AMOVHZ:
3652 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3653 case AMOVB, AMOVBZ:
3654 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3655 adj := uint32(0)
3656 if i2&1 != 0 {
3657 i2 -= 1
3658 adj = 1
3659 }
3660 switch p.As {
3661 case AMOVB:
3662 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3663 case AMOVBZ:
3664 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3665 }
3666 case AFMOVD:
3667 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3668 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3669 case AFMOVS:
3670 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3671 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3672 }
3673 c.addrilreloc(p.From.Sym, int64(i2))
3674
3675 case 76:
3676 zRR(op_SPM, uint32(p.From.Reg), 0, asm)
3677
3678 case 77:
3679 if p.From.Offset > 255 || p.From.Offset < 1 {
3680 c.ctxt.Diag("illegal system call; system call number out of range: %v", p)
3681 zE(op_TRAP2, asm)
3682 } else {
3683 zI(op_SVC, uint32(p.From.Offset), asm)
3684 }
3685
3686 case 78:
3687
3688
3689 *asm = append(*asm, 0, 0, 0, 0)
3690
3691 case 79:
3692 v := c.regoff(&p.To)
3693 if v < 0 {
3694 v = 0
3695 }
3696 if p.As == ACS {
3697 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3698 } else if p.As == ACSG {
3699 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3700 }
3701
3702 case 80:
3703 zRR(op_BCR, 14, 0, asm)
3704
3705 case 81:
3706 switch p.As {
3707 case ALDGR:
3708 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3709 case ALGDR:
3710 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3711 }
3712
3713 case 82:
3714 var opcode uint32
3715 switch p.As {
3716 default:
3717 log.Fatalf("unexpected opcode %v", p.As)
3718 case ACEFBRA:
3719 opcode = op_CEFBRA
3720 case ACDFBRA:
3721 opcode = op_CDFBRA
3722 case ACEGBRA:
3723 opcode = op_CEGBRA
3724 case ACDGBRA:
3725 opcode = op_CDGBRA
3726 case ACELFBR:
3727 opcode = op_CELFBR
3728 case ACDLFBR:
3729 opcode = op_CDLFBR
3730 case ACELGBR:
3731 opcode = op_CELGBR
3732 case ACDLGBR:
3733 opcode = op_CDLGBR
3734 }
3735
3736
3737
3738
3739 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3740
3741 case 83:
3742 var opcode uint32
3743 switch p.As {
3744 default:
3745 log.Fatalf("unexpected opcode %v", p.As)
3746 case ACFEBRA:
3747 opcode = op_CFEBRA
3748 case ACFDBRA:
3749 opcode = op_CFDBRA
3750 case ACGEBRA:
3751 opcode = op_CGEBRA
3752 case ACGDBRA:
3753 opcode = op_CGDBRA
3754 case ACLFEBR:
3755 opcode = op_CLFEBR
3756 case ACLFDBR:
3757 opcode = op_CLFDBR
3758 case ACLGEBR:
3759 opcode = op_CLGEBR
3760 case ACLGDBR:
3761 opcode = op_CLGDBR
3762 }
3763
3764
3765 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3766
3767 case 84:
3768 l := c.regoff(&p.From)
3769 if l < 1 || l > 256 {
3770 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3771 }
3772 if p.GetFrom3().Index != 0 || p.To.Index != 0 {
3773 c.ctxt.Diag("cannot use index reg")
3774 }
3775 b1 := p.To.Reg
3776 b2 := p.GetFrom3().Reg
3777 if b1 == 0 {
3778 b1 = REGSP
3779 }
3780 if b2 == 0 {
3781 b2 = REGSP
3782 }
3783 d1 := c.regoff(&p.To)
3784 d2 := c.regoff(p.GetFrom3())
3785 if d1 < 0 || d1 >= DISP12 {
3786 if b2 == int16(regtmp(p)) {
3787 c.ctxt.Diag("regtmp(p) conflict")
3788 }
3789 if b1 != int16(regtmp(p)) {
3790 zRRE(op_LGR, regtmp(p), uint32(b1), asm)
3791 }
3792 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm)
3793 if d1 == d2 && b1 == b2 {
3794 d2 = 0
3795 b2 = int16(regtmp(p))
3796 }
3797 d1 = 0
3798 b1 = int16(regtmp(p))
3799 }
3800 if d2 < 0 || d2 >= DISP12 {
3801 if b1 == REGTMP2 {
3802 c.ctxt.Diag("REGTMP2 conflict")
3803 }
3804 if b2 != REGTMP2 {
3805 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3806 }
3807 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3808 d2 = 0
3809 b2 = REGTMP2
3810 }
3811 var opcode uint32
3812 switch p.As {
3813 default:
3814 c.ctxt.Diag("unexpected opcode %v", p.As)
3815 case AMVC:
3816 opcode = op_MVC
3817 case AMVCIN:
3818 opcode = op_MVCIN
3819 case ACLC:
3820 opcode = op_CLC
3821
3822 b1, b2 = b2, b1
3823 d1, d2 = d2, d1
3824 case AXC:
3825 opcode = op_XC
3826 case AOC:
3827 opcode = op_OC
3828 case ANC:
3829 opcode = op_NC
3830 }
3831 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3832
3833 case 85:
3834 v := c.regoff(&p.From)
3835 if p.From.Sym == nil {
3836 if (v & 1) != 0 {
3837 c.ctxt.Diag("cannot use LARL with odd offset: %v", v)
3838 }
3839 } else {
3840 c.addrilreloc(p.From.Sym, int64(v))
3841 v = 0
3842 }
3843 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3844
3845 case 86:
3846 d := c.vregoff(&p.From)
3847 x := p.From.Index
3848 b := p.From.Reg
3849 if b == 0 {
3850 b = REGSP
3851 }
3852 switch p.As {
3853 case ALA:
3854 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3855 case ALAY:
3856 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3857 }
3858
3859 case 87:
3860 v := c.vregoff(&p.From)
3861 if p.From.Sym == nil {
3862 if v&1 != 0 {
3863 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3864 }
3865 } else {
3866 c.addrilreloc(p.From.Sym, v)
3867 v = 0
3868 }
3869 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3870
3871 case 88:
3872 var opcode uint32
3873 switch p.As {
3874 case ASTCK:
3875 opcode = op_STCK
3876 case ASTCKC:
3877 opcode = op_STCKC
3878 case ASTCKE:
3879 opcode = op_STCKE
3880 case ASTCKF:
3881 opcode = op_STCKF
3882 }
3883 v := c.vregoff(&p.To)
3884 r := p.To.Reg
3885 if r == 0 {
3886 r = REGSP
3887 }
3888 zS(opcode, uint32(r), uint32(v), asm)
3889
3890 case 89:
3891 var v int32
3892 if p.To.Target() != nil {
3893 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3894 }
3895
3896
3897 r1, r2 := p.From.Reg, p.Reg
3898 if p.From.Type == obj.TYPE_CONST {
3899 r1, r2 = p.Reg, p.RestArgs[0].Reg
3900 }
3901 m3 := uint32(c.branchMask(p))
3902
3903 var opcode uint32
3904 switch p.As {
3905 case ACRJ:
3906
3907 opcode = op_CRJ
3908 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3909
3910 opcode = op_CGRJ
3911 case ACLRJ:
3912
3913 opcode = op_CLRJ
3914 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3915
3916 opcode = op_CLGRJ
3917 }
3918
3919 if int32(int16(v)) != v {
3920
3921
3922
3923
3924
3925
3926
3927
3928 m3 ^= 0xe
3929 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm)
3930 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3931 } else {
3932 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm)
3933 }
3934
3935 case 90:
3936 var v int32
3937 if p.To.Target() != nil {
3938 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3939 }
3940
3941
3942 r1, i2 := p.From.Reg, p.RestArgs[0].Offset
3943 if p.From.Type == obj.TYPE_CONST {
3944 r1 = p.Reg
3945 }
3946 m3 := uint32(c.branchMask(p))
3947
3948 var opcode uint32
3949 switch p.As {
3950 case ACIJ:
3951 opcode = op_CIJ
3952 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3953 opcode = op_CGIJ
3954 case ACLIJ:
3955 opcode = op_CLIJ
3956 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3957 opcode = op_CLGIJ
3958 }
3959 if int32(int16(v)) != v {
3960
3961
3962
3963
3964
3965
3966
3967
3968 m3 ^= 0xe
3969 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm)
3970 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3971 } else {
3972 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm)
3973 }
3974
3975 case 91:
3976 var opcode uint32
3977 switch p.As {
3978 case ATMHH:
3979 opcode = op_TMHH
3980 case ATMHL:
3981 opcode = op_TMHL
3982 case ATMLH:
3983 opcode = op_TMLH
3984 case ATMLL:
3985 opcode = op_TMLL
3986 }
3987 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
3988
3989 case 92:
3990 zRRE(op_IPM, uint32(p.From.Reg), 0, asm)
3991
3992 case 93:
3993 v := c.vregoff(&p.To)
3994 if v != 0 {
3995 c.ctxt.Diag("invalid offset against GOT slot %v", p)
3996 }
3997 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3998 rel := obj.Addrel(c.cursym)
3999 rel.Off = int32(c.pc + 2)
4000 rel.Siz = 4
4001 rel.Sym = p.From.Sym
4002 rel.Type = objabi.R_GOTPCREL
4003 rel.Add = 2 + int64(rel.Siz)
4004
4005 case 94:
4006 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm)
4007 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4008 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
4009 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
4010 rel := obj.Addrel(c.cursym)
4011 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI)
4012 rel.Siz = 8
4013 rel.Sym = p.From.Sym
4014 rel.Type = objabi.R_TLS_LE
4015 rel.Add = 0
4016
4017 case 95:
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029 zRIL(_b, op_LARL, regtmp(p), 0, asm)
4030 ieent := obj.Addrel(c.cursym)
4031 ieent.Off = int32(c.pc + 2)
4032 ieent.Siz = 4
4033 ieent.Sym = p.From.Sym
4034 ieent.Type = objabi.R_TLS_IE
4035 ieent.Add = 2 + int64(ieent.Siz)
4036
4037
4038 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4039
4040
4041
4042 case 96:
4043 length := c.vregoff(&p.From)
4044 offset := c.vregoff(&p.To)
4045 reg := p.To.Reg
4046 if reg == 0 {
4047 reg = REGSP
4048 }
4049 if length <= 0 {
4050 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
4051 }
4052 for length > 0 {
4053 if offset < 0 || offset >= DISP12 {
4054 if offset >= -DISP20/2 && offset < DISP20/2 {
4055 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm)
4056 } else {
4057 if reg != int16(regtmp(p)) {
4058 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4059 }
4060 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4061 }
4062 reg = int16(regtmp(p))
4063 offset = 0
4064 }
4065 size := length
4066 if size > 256 {
4067 size = 256
4068 }
4069
4070 switch size {
4071 case 1:
4072 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
4073 case 2:
4074 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
4075 case 4:
4076 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
4077 case 8:
4078 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
4079 default:
4080 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
4081 }
4082
4083 length -= size
4084 offset += size
4085 }
4086
4087 case 97:
4088 rstart := p.From.Reg
4089 rend := p.Reg
4090 offset := c.regoff(&p.To)
4091 reg := p.To.Reg
4092 if reg == 0 {
4093 reg = REGSP
4094 }
4095 if offset < -DISP20/2 || offset >= DISP20/2 {
4096 if reg != int16(regtmp(p)) {
4097 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4098 }
4099 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4100 reg = int16(regtmp(p))
4101 offset = 0
4102 }
4103 switch p.As {
4104 case ASTMY:
4105 if offset >= 0 && offset < DISP12 {
4106 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4107 } else {
4108 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4109 }
4110 case ASTMG:
4111 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4112 }
4113
4114 case 98:
4115 rstart := p.Reg
4116 rend := p.To.Reg
4117 offset := c.regoff(&p.From)
4118 reg := p.From.Reg
4119 if reg == 0 {
4120 reg = REGSP
4121 }
4122 if offset < -DISP20/2 || offset >= DISP20/2 {
4123 if reg != int16(regtmp(p)) {
4124 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4125 }
4126 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4127 reg = int16(regtmp(p))
4128 offset = 0
4129 }
4130 switch p.As {
4131 case ALMY:
4132 if offset >= 0 && offset < DISP12 {
4133 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4134 } else {
4135 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4136 }
4137 case ALMG:
4138 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4139 }
4140
4141 case 99:
4142 if p.To.Index != 0 {
4143 c.ctxt.Diag("cannot use indexed address")
4144 }
4145 offset := c.regoff(&p.To)
4146 if offset < -DISP20/2 || offset >= DISP20/2 {
4147 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset)
4148 }
4149 var opcode uint32
4150 switch p.As {
4151 case ALAA:
4152 opcode = op_LAA
4153 case ALAAG:
4154 opcode = op_LAAG
4155 case ALAAL:
4156 opcode = op_LAAL
4157 case ALAALG:
4158 opcode = op_LAALG
4159 case ALAN:
4160 opcode = op_LAN
4161 case ALANG:
4162 opcode = op_LANG
4163 case ALAX:
4164 opcode = op_LAX
4165 case ALAXG:
4166 opcode = op_LAXG
4167 case ALAO:
4168 opcode = op_LAO
4169 case ALAOG:
4170 opcode = op_LAOG
4171 }
4172 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm)
4173
4174 case 100:
4175 op, m3, _ := vop(p.As)
4176 v1 := p.From.Reg
4177 if p.Reg != 0 {
4178 m3 = uint32(c.vregoff(&p.From))
4179 v1 = p.Reg
4180 }
4181 b2 := p.To.Reg
4182 if b2 == 0 {
4183 b2 = REGSP
4184 }
4185 d2 := uint32(c.vregoff(&p.To))
4186 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4187
4188 case 101:
4189 op, m3, _ := vop(p.As)
4190 src := &p.From
4191 if p.GetFrom3() != nil {
4192 m3 = uint32(c.vregoff(&p.From))
4193 src = p.GetFrom3()
4194 }
4195 b2 := src.Reg
4196 if b2 == 0 {
4197 b2 = REGSP
4198 }
4199 d2 := uint32(c.vregoff(src))
4200 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm)
4201
4202 case 102:
4203 op, _, _ := vop(p.As)
4204 m3 := uint32(c.vregoff(&p.From))
4205 b2 := p.To.Reg
4206 if b2 == 0 {
4207 b2 = REGSP
4208 }
4209 d2 := uint32(c.vregoff(&p.To))
4210 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4211
4212 case 103:
4213 op, _, _ := vop(p.As)
4214 m3 := uint32(c.vregoff(&p.From))
4215 b2 := p.GetFrom3().Reg
4216 if b2 == 0 {
4217 b2 = REGSP
4218 }
4219 d2 := uint32(c.vregoff(p.GetFrom3()))
4220 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm)
4221
4222 case 104:
4223 op, m4, _ := vop(p.As)
4224 fr := p.Reg
4225 if fr == 0 {
4226 fr = p.To.Reg
4227 }
4228 bits := uint32(c.vregoff(&p.From))
4229 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
4230
4231 case 105:
4232 op, _, _ := vop(p.As)
4233 offset := uint32(c.vregoff(&p.To))
4234 reg := p.To.Reg
4235 if reg == 0 {
4236 reg = REGSP
4237 }
4238 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
4239
4240 case 106:
4241 op, _, _ := vop(p.As)
4242 offset := uint32(c.vregoff(&p.From))
4243 reg := p.From.Reg
4244 if reg == 0 {
4245 reg = REGSP
4246 }
4247 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
4248
4249 case 107:
4250 op, _, _ := vop(p.As)
4251 offset := uint32(c.vregoff(&p.To))
4252 reg := p.To.Reg
4253 if reg == 0 {
4254 reg = REGSP
4255 }
4256 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4257
4258 case 108:
4259 op, _, _ := vop(p.As)
4260 offset := uint32(c.vregoff(p.GetFrom3()))
4261 reg := p.GetFrom3().Reg
4262 if reg == 0 {
4263 reg = REGSP
4264 }
4265 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4266
4267 case 109:
4268 op, m3, _ := vop(p.As)
4269 i2 := uint32(c.vregoff(&p.From))
4270 if p.GetFrom3() != nil {
4271 m3 = uint32(c.vregoff(&p.From))
4272 i2 = uint32(c.vregoff(p.GetFrom3()))
4273 }
4274 switch p.As {
4275 case AVZERO:
4276 i2 = 0
4277 case AVONE:
4278 i2 = 0xffff
4279 }
4280 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
4281
4282 case 110:
4283 op, m4, _ := vop(p.As)
4284 i2 := uint32(c.vregoff(&p.From))
4285 i3 := uint32(c.vregoff(p.GetFrom3()))
4286 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
4287
4288 case 111:
4289 op, m4, _ := vop(p.As)
4290 i2 := uint32(c.vregoff(&p.From))
4291 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
4292
4293 case 112:
4294 op, m5, _ := vop(p.As)
4295 i4 := uint32(c.vregoff(&p.From))
4296 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm)
4297
4298 case 113:
4299 op, m4, _ := vop(p.As)
4300 m5 := singleElementMask(p.As)
4301 i3 := uint32(c.vregoff(&p.From))
4302 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
4303
4304 case 114:
4305 op, m3, m5 := vop(p.As)
4306 m4 := singleElementMask(p.As)
4307 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
4308
4309 case 115:
4310 op, m3, m5 := vop(p.As)
4311 m4 := singleElementMask(p.As)
4312 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
4313
4314 case 117:
4315 op, m4, m5 := vop(p.As)
4316 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
4317
4318 case 118:
4319 op, m4, m6 := vop(p.As)
4320 m5 := singleElementMask(p.As)
4321 v3 := p.Reg
4322 if v3 == 0 {
4323 v3 = p.To.Reg
4324 }
4325 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
4326
4327 case 119:
4328 op, m4, m6 := vop(p.As)
4329 m5 := singleElementMask(p.As)
4330 v2 := p.Reg
4331 if v2 == 0 {
4332 v2 = p.To.Reg
4333 }
4334 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
4335
4336 case 120:
4337 op, m6, _ := vop(p.As)
4338 m5 := singleElementMask(p.As)
4339 v1 := uint32(p.To.Reg)
4340 v2 := uint32(p.From.Reg)
4341 v3 := uint32(p.Reg)
4342 v4 := uint32(p.GetFrom3().Reg)
4343 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
4344
4345 case 121:
4346 op, m6, _ := vop(p.As)
4347 m5 := singleElementMask(p.As)
4348 v1 := uint32(p.To.Reg)
4349 v2 := uint32(p.From.Reg)
4350 v3 := uint32(p.Reg)
4351 v4 := uint32(p.GetFrom3().Reg)
4352 zVRRe(op, v1, v2, v3, m6, m5, v4, asm)
4353
4354 case 122:
4355 op, _, _ := vop(p.As)
4356 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
4357
4358 case 123:
4359 op, _, _ := vop(p.As)
4360 m4 := c.regoff(&p.From)
4361 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm)
4362 }
4363 }
4364
4365 func (c *ctxtz) vregoff(a *obj.Addr) int64 {
4366 c.instoffset = 0
4367 if a != nil {
4368 c.aclass(a)
4369 }
4370 return c.instoffset
4371 }
4372
4373 func (c *ctxtz) regoff(a *obj.Addr) int32 {
4374 return int32(c.vregoff(a))
4375 }
4376
4377
4378 func isU12(displacement int32) bool {
4379 return displacement >= 0 && displacement < DISP12
4380 }
4381
4382
4383 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) {
4384 switch a {
4385 case AFMOVD:
4386 return op_LD, true
4387 case AFMOVS:
4388 return op_LE, true
4389 }
4390 return 0, false
4391 }
4392
4393
4394 func (c *ctxtz) zopload(a obj.As) uint32 {
4395 switch a {
4396
4397 case AMOVD:
4398 return op_LG
4399 case AMOVW:
4400 return op_LGF
4401 case AMOVWZ:
4402 return op_LLGF
4403 case AMOVH:
4404 return op_LGH
4405 case AMOVHZ:
4406 return op_LLGH
4407 case AMOVB:
4408 return op_LGB
4409 case AMOVBZ:
4410 return op_LLGC
4411
4412
4413 case AFMOVD:
4414 return op_LDY
4415 case AFMOVS:
4416 return op_LEY
4417
4418
4419 case AMOVDBR:
4420 return op_LRVG
4421 case AMOVWBR:
4422 return op_LRV
4423 case AMOVHBR:
4424 return op_LRVH
4425 }
4426
4427 c.ctxt.Diag("unknown store opcode %v", a)
4428 return 0
4429 }
4430
4431
4432 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) {
4433 switch a {
4434 case AFMOVD:
4435 return op_STD, true
4436 case AFMOVS:
4437 return op_STE, true
4438 case AMOVW, AMOVWZ:
4439 return op_ST, true
4440 case AMOVH, AMOVHZ:
4441 return op_STH, true
4442 case AMOVB, AMOVBZ:
4443 return op_STC, true
4444 }
4445 return 0, false
4446 }
4447
4448
4449 func (c *ctxtz) zopstore(a obj.As) uint32 {
4450 switch a {
4451
4452 case AMOVD:
4453 return op_STG
4454 case AMOVW, AMOVWZ:
4455 return op_STY
4456 case AMOVH, AMOVHZ:
4457 return op_STHY
4458 case AMOVB, AMOVBZ:
4459 return op_STCY
4460
4461
4462 case AFMOVD:
4463 return op_STDY
4464 case AFMOVS:
4465 return op_STEY
4466
4467
4468 case AMOVDBR:
4469 return op_STRVG
4470 case AMOVWBR:
4471 return op_STRV
4472 case AMOVHBR:
4473 return op_STRVH
4474 }
4475
4476 c.ctxt.Diag("unknown store opcode %v", a)
4477 return 0
4478 }
4479
4480
4481 func (c *ctxtz) zoprre(a obj.As) uint32 {
4482 switch a {
4483 case ACMP:
4484 return op_CGR
4485 case ACMPU:
4486 return op_CLGR
4487 case AFCMPO:
4488 return op_KDBR
4489 case AFCMPU:
4490 return op_CDBR
4491 case ACEBR:
4492 return op_CEBR
4493 }
4494 c.ctxt.Diag("unknown rre opcode %v", a)
4495 return 0
4496 }
4497
4498
4499 func (c *ctxtz) zoprr(a obj.As) uint32 {
4500 switch a {
4501 case ACMPW:
4502 return op_CR
4503 case ACMPWU:
4504 return op_CLR
4505 }
4506 c.ctxt.Diag("unknown rr opcode %v", a)
4507 return 0
4508 }
4509
4510
4511 func (c *ctxtz) zopril(a obj.As) uint32 {
4512 switch a {
4513 case ACMP:
4514 return op_CGFI
4515 case ACMPU:
4516 return op_CLGFI
4517 case ACMPW:
4518 return op_CFI
4519 case ACMPWU:
4520 return op_CLFI
4521 }
4522 c.ctxt.Diag("unknown ril opcode %v", a)
4523 return 0
4524 }
4525
4526
4527 const (
4528 sizeE = 2
4529 sizeI = 2
4530 sizeIE = 4
4531 sizeMII = 6
4532 sizeRI = 4
4533 sizeRI1 = 4
4534 sizeRI2 = 4
4535 sizeRI3 = 4
4536 sizeRIE = 6
4537 sizeRIE1 = 6
4538 sizeRIE2 = 6
4539 sizeRIE3 = 6
4540 sizeRIE4 = 6
4541 sizeRIE5 = 6
4542 sizeRIE6 = 6
4543 sizeRIL = 6
4544 sizeRIL1 = 6
4545 sizeRIL2 = 6
4546 sizeRIL3 = 6
4547 sizeRIS = 6
4548 sizeRR = 2
4549 sizeRRD = 4
4550 sizeRRE = 4
4551 sizeRRF = 4
4552 sizeRRF1 = 4
4553 sizeRRF2 = 4
4554 sizeRRF3 = 4
4555 sizeRRF4 = 4
4556 sizeRRF5 = 4
4557 sizeRRR = 2
4558 sizeRRS = 6
4559 sizeRS = 4
4560 sizeRS1 = 4
4561 sizeRS2 = 4
4562 sizeRSI = 4
4563 sizeRSL = 6
4564 sizeRSY = 6
4565 sizeRSY1 = 6
4566 sizeRSY2 = 6
4567 sizeRX = 4
4568 sizeRX1 = 4
4569 sizeRX2 = 4
4570 sizeRXE = 6
4571 sizeRXF = 6
4572 sizeRXY = 6
4573 sizeRXY1 = 6
4574 sizeRXY2 = 6
4575 sizeS = 4
4576 sizeSI = 4
4577 sizeSIL = 6
4578 sizeSIY = 6
4579 sizeSMI = 6
4580 sizeSS = 6
4581 sizeSS1 = 6
4582 sizeSS2 = 6
4583 sizeSS3 = 6
4584 sizeSS4 = 6
4585 sizeSS5 = 6
4586 sizeSS6 = 6
4587 sizeSSE = 6
4588 sizeSSF = 6
4589 )
4590
4591
4592 type form int
4593
4594 const (
4595 _a form = iota
4596 _b
4597 _c
4598 _d
4599 _e
4600 _f
4601 )
4602
4603 func zE(op uint32, asm *[]byte) {
4604 *asm = append(*asm, uint8(op>>8), uint8(op))
4605 }
4606
4607 func zI(op, i1 uint32, asm *[]byte) {
4608 *asm = append(*asm, uint8(op>>8), uint8(i1))
4609 }
4610
4611 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) {
4612 *asm = append(*asm,
4613 uint8(op>>8),
4614 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F),
4615 uint8(ri2),
4616 uint8(ri3>>16),
4617 uint8(ri3>>8),
4618 uint8(ri3))
4619 }
4620
4621 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4622 *asm = append(*asm,
4623 uint8(op>>8),
4624 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4625 uint8(i2_ri2>>8),
4626 uint8(i2_ri2))
4627 }
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4641 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4642
4643 switch f {
4644 default:
4645 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4646 case _f:
4647 *asm = append(*asm, uint8(i3), uint8(i4))
4648 }
4649
4650 switch f {
4651 case _a, _b:
4652 *asm = append(*asm, uint8(m3)<<4)
4653 default:
4654 *asm = append(*asm, uint8(i2_i5))
4655 }
4656
4657 *asm = append(*asm, uint8(op))
4658 }
4659
4660 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4661 if f == _a || f == _b {
4662 r1_m1 = r1_m1 - obj.RBaseS390X
4663 }
4664 *asm = append(*asm,
4665 uint8(op>>8),
4666 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4667 uint8(i2_ri2>>24),
4668 uint8(i2_ri2>>16),
4669 uint8(i2_ri2>>8),
4670 uint8(i2_ri2))
4671 }
4672
4673 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) {
4674 *asm = append(*asm,
4675 uint8(op>>8),
4676 (uint8(r1)<<4)|uint8(m3&0x0F),
4677 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F),
4678 uint8(d4),
4679 uint8(i2),
4680 uint8(op))
4681 }
4682
4683 func zRR(op, r1, r2 uint32, asm *[]byte) {
4684 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4685 }
4686
4687 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4688 *asm = append(*asm,
4689 uint8(op>>8),
4690 uint8(op),
4691 uint8(r1)<<4,
4692 (uint8(r3)<<4)|uint8(r2&0x0F))
4693 }
4694
4695 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4696 *asm = append(*asm,
4697 uint8(op>>8),
4698 uint8(op),
4699 0,
4700 (uint8(r1)<<4)|uint8(r2&0x0F))
4701 }
4702
4703 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4704 *asm = append(*asm,
4705 uint8(op>>8),
4706 uint8(op),
4707 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4708 (uint8(r1)<<4)|uint8(r2&0x0F))
4709 }
4710
4711 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) {
4712 *asm = append(*asm,
4713 uint8(op>>8),
4714 (uint8(r1)<<4)|uint8(r2&0x0F),
4715 (uint8(b4)<<4)|uint8((d4>>8)&0x0F),
4716 uint8(d4),
4717 uint8(m3)<<4,
4718 uint8(op))
4719 }
4720
4721 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4722 *asm = append(*asm,
4723 uint8(op>>8),
4724 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4725 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4726 uint8(d2))
4727 }
4728
4729 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) {
4730 *asm = append(*asm,
4731 uint8(op>>8),
4732 (uint8(r1)<<4)|uint8(r3&0x0F),
4733 uint8(ri2>>8),
4734 uint8(ri2))
4735 }
4736
4737 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) {
4738 *asm = append(*asm,
4739 uint8(op>>8),
4740 uint8(l1),
4741 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4742 uint8(d2),
4743 uint8(op))
4744 }
4745
4746 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4747 dl2 := uint16(d2) & 0x0FFF
4748 *asm = append(*asm,
4749 uint8(op>>8),
4750 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4751 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4752 uint8(dl2),
4753 uint8(d2>>12),
4754 uint8(op))
4755 }
4756
4757 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4758 *asm = append(*asm,
4759 uint8(op>>8),
4760 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4761 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4762 uint8(d2))
4763 }
4764
4765 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4766 *asm = append(*asm,
4767 uint8(op>>8),
4768 (uint8(r1)<<4)|uint8(x2&0x0F),
4769 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4770 uint8(d2),
4771 uint8(m3)<<4,
4772 uint8(op))
4773 }
4774
4775 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) {
4776 *asm = append(*asm,
4777 uint8(op>>8),
4778 (uint8(r3)<<4)|uint8(x2&0x0F),
4779 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4780 uint8(d2),
4781 uint8(m1)<<4,
4782 uint8(op))
4783 }
4784
4785 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4786 dl2 := uint16(d2) & 0x0FFF
4787 *asm = append(*asm,
4788 uint8(op>>8),
4789 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4790 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4791 uint8(dl2),
4792 uint8(d2>>12),
4793 uint8(op))
4794 }
4795
4796 func zS(op, b2, d2 uint32, asm *[]byte) {
4797 *asm = append(*asm,
4798 uint8(op>>8),
4799 uint8(op),
4800 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4801 uint8(d2))
4802 }
4803
4804 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4805 *asm = append(*asm,
4806 uint8(op>>8),
4807 uint8(i2),
4808 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4809 uint8(d1))
4810 }
4811
4812 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4813 *asm = append(*asm,
4814 uint8(op>>8),
4815 uint8(op),
4816 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4817 uint8(d1),
4818 uint8(i2>>8),
4819 uint8(i2))
4820 }
4821
4822 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4823 dl1 := uint16(d1) & 0x0FFF
4824 *asm = append(*asm,
4825 uint8(op>>8),
4826 uint8(i2),
4827 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4828 uint8(dl1),
4829 uint8(d1>>12),
4830 uint8(op))
4831 }
4832
4833 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) {
4834 *asm = append(*asm,
4835 uint8(op>>8),
4836 uint8(m1)<<4,
4837 (uint8(b3)<<4)|uint8((d3>>8)&0x0F),
4838 uint8(d3),
4839 uint8(ri2>>8),
4840 uint8(ri2))
4841 }
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4854 *asm = append(*asm, uint8(op>>8))
4855
4856 switch f {
4857 case _a:
4858 *asm = append(*asm, uint8(l1_r1))
4859 case _b, _c, _d, _e:
4860 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4861 case _f:
4862 *asm = append(*asm, uint8(l2_i3_r3))
4863 }
4864
4865 *asm = append(*asm,
4866 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4867 uint8(d1_d2),
4868 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4869 uint8(d2_d4))
4870 }
4871
4872 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) {
4873 *asm = append(*asm,
4874 uint8(op>>8),
4875 uint8(op),
4876 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4877 uint8(d1),
4878 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4879 uint8(d2))
4880 }
4881
4882 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) {
4883 *asm = append(*asm,
4884 uint8(op>>8),
4885 (uint8(r3)<<4)|(uint8(op)&0x0F),
4886 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4887 uint8(d1),
4888 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4889 uint8(d2))
4890 }
4891
4892 func rxb(va, vb, vc, vd uint32) uint8 {
4893 mask := uint8(0)
4894 if va >= REG_V16 && va <= REG_V31 {
4895 mask |= 0x8
4896 }
4897 if vb >= REG_V16 && vb <= REG_V31 {
4898 mask |= 0x4
4899 }
4900 if vc >= REG_V16 && vc <= REG_V31 {
4901 mask |= 0x2
4902 }
4903 if vd >= REG_V16 && vd <= REG_V31 {
4904 mask |= 0x1
4905 }
4906 return mask
4907 }
4908
4909 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
4910 *asm = append(*asm,
4911 uint8(op>>8),
4912 (uint8(v1)<<4)|(uint8(x2)&0xf),
4913 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4914 uint8(d2),
4915 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
4916 uint8(op))
4917 }
4918
4919 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
4920 *asm = append(*asm,
4921 uint8(op>>8),
4922 (uint8(v1)<<4)|(uint8(v2)&0xf),
4923 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4924 uint8(d2),
4925 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4926 uint8(op))
4927 }
4928
4929 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
4930 *asm = append(*asm,
4931 uint8(op>>8),
4932 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
4933 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4934 uint8(d2),
4935 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
4936 uint8(op))
4937 }
4938
4939 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
4940 *asm = append(*asm,
4941 uint8(op>>8),
4942 (uint8(v1)<<4)|(uint8(v2)&0xf),
4943 0,
4944 (uint8(m5)<<4)|(uint8(m4)&0xf),
4945 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4946 uint8(op))
4947 }
4948
4949 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
4950 *asm = append(*asm,
4951 uint8(op>>8),
4952 (uint8(v1)<<4)|(uint8(v2)&0xf),
4953 uint8(v3)<<4,
4954 uint8(m5)<<4,
4955 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
4956 uint8(op))
4957 }
4958
4959 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
4960 *asm = append(*asm,
4961 uint8(op>>8),
4962 (uint8(v1)<<4)|(uint8(v2)&0xf),
4963 uint8(v3)<<4,
4964 (uint8(m6)<<4)|(uint8(m5)&0xf),
4965 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
4966 uint8(op))
4967 }
4968
4969 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
4970 *asm = append(*asm,
4971 uint8(op>>8),
4972 (uint8(v1)<<4)|(uint8(v2)&0xf),
4973 (uint8(v3)<<4)|(uint8(m5)&0xf),
4974 uint8(m6)<<4,
4975 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
4976 uint8(op))
4977 }
4978
4979 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
4980 *asm = append(*asm,
4981 uint8(op>>8),
4982 (uint8(v1)<<4)|(uint8(v2)&0xf),
4983 (uint8(v3)<<4)|(uint8(m6)&0xf),
4984 uint8(m5),
4985 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
4986 uint8(op))
4987 }
4988
4989 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
4990 *asm = append(*asm,
4991 uint8(op>>8),
4992 (uint8(v1)<<4)|(uint8(r2)&0xf),
4993 uint8(r3)<<4,
4994 0,
4995 rxb(v1, 0, 0, 0),
4996 uint8(op))
4997 }
4998
4999 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
5000 *asm = append(*asm,
5001 uint8(op>>8),
5002 uint8(v1)<<4,
5003 uint8(i2>>8),
5004 uint8(i2),
5005 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5006 uint8(op))
5007 }
5008
5009 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
5010 *asm = append(*asm,
5011 uint8(op>>8),
5012 uint8(v1)<<4,
5013 uint8(i2),
5014 uint8(i3),
5015 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
5016 uint8(op))
5017 }
5018
5019 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
5020 *asm = append(*asm,
5021 uint8(op>>8),
5022 (uint8(v1)<<4)|(uint8(v3)&0xf),
5023 uint8(i2>>8),
5024 uint8(i2),
5025 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
5026 uint8(op))
5027 }
5028
5029 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
5030 *asm = append(*asm,
5031 uint8(op>>8),
5032 (uint8(v1)<<4)|(uint8(v2)&0xf),
5033 uint8(v3)<<4,
5034 uint8(i4),
5035 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
5036 uint8(op))
5037 }
5038
5039 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
5040 *asm = append(*asm,
5041 uint8(op>>8),
5042 (uint8(v1)<<4)|(uint8(v2)&0xf),
5043 uint8(i3>>4),
5044 (uint8(i3)<<4)|(uint8(m5)&0xf),
5045 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),
5046 uint8(op))
5047 }
5048
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